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xSPI - PSRAM Master
Arasan Chip System’s xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports the xSPI JESD~251 standard from a standard AXI3 or AXI4 slave interface. It also supports HyperRAM, HyperFlash, and features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces.
The xSPI/PSRAM master IP is designed so that a user design may immediately access memory from the xSPI device in SPI mode, or alternatively issue a command to switch to any other mode. Additionally, a DMA command may be issued to copy memory to or from the xSPI device and anywhere else on the system bus.
The xSPI/PSRAM master IP is designed so that a user design may immediately access memory from the xSPI device in SPI mode, or alternatively issue a command to switch to any other mode. Additionally, a DMA command may be issued to copy memory to or from the xSPI device and anywhere else on the system bus.
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Block Diagram of the xSPI - PSRAM Master IP Core
