XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 family of cores covers a wide range of area / throughput combinations using both 256 and 128-bit keys, allowing the designer to choose the smallest core that satisfies the desired clock/throughput requirements. XTS2 is similar to XTS3, but supports only 128-bit keys. Each core contains the base AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in both source and netlist form.
- Key Features Small size: XTS2-12.8 starts at less than 30,000 ASIC gates and delivers throughput of 7 Gbps. XTS3-18.2 starts at 44,000 ASIC gates at throughput of 18.2 bits per clock. The fastest cores in the families, XTS2-128 and XTS3-128, deliver 128 bits of throughput per clock (for example, at 500 MHz clock the maximum throughput is 64 Gbps).
- Completely self-contained: does not require external memory
- Supports both encryption and decryption
- Includes key expansion and CTS support
- Supports XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) (XTS) mode encryption and decryption
- 128+128 and 256+256 bit AES keys supported.
- Easily parallelizable for even higher data rates
- Flow-through design
- Test bench provided
- Designer can choose a core from the family to precisely target the required throughput.
- HDL Source Licenses
- Synthesizable Verilog RTL source code
- Verilog testbench (self-checking)
- Vectors for testbench
- Expected results
- User Documentation
- Netlist Licenses
- Post-synthesis EDIF
- Testbench (self-checking)
- Vectors for testbenches
- Expected results
- Hard drive encryption compliant with the IEEE P1619 and NIST SP800-38E draft
Block Diagram of the XTS-AES IEEE P1619 Core Families IP Core