The ability to purchase Zynq BFM has been discontinued as of December 1, 2016. The existing AXI-BFM licenses will work perpetually in releases through 2016.4, but will not be supported after the Vivado 2016.4 release.
Zynq BFM will be replaced by Xilinx Zynq Verification IP in CY2017. For more information please contact your Local Xilinx Sales Contact.
- Pin compatible and Verilog Based simulation model
- Supports all AXI interfaces
- AXI 3.0 compliant
- Sparse memory model (for DDR) and a RAM model (for OCM)
- Verilog task-based API
- Delivered in Vivado® Design Suite
- Blocking and non-blocking interrupt support
- Requires license to AXI BFM models