Industry Articles
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How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it
(Monday, August 31, 2020)
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Super Edge Medical SoC (SEMC)
(Thursday, August 27, 2020)
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Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors
(Monday, August 24, 2020)
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Optimization of Crosstalk Delta Delay on Clock Nets
(Monday, August 24, 2020)
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Simplifying AC and DC data acquisition signal chains
(Thursday, August 13, 2020)
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Bounds in Placement
(Monday, August 10, 2020)
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Automotive Design Needs Efficient Verification to Survive
(Wednesday, July 29, 2020)
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The Quantum Tunneling Mechanism of NeoPUF
(Tuesday, July 28, 2020)
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DDR IP Hardening - Overview & Advance Tips
(Monday, July 27, 2020)
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AI Edge Inference is Totally Different to Data Center
(Thursday, July 23, 2020)
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At the edge of data processing
(Monday, July 20, 2020)
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Scan Chains: PnR Outlook
(Monday, July 20, 2020)
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Part 2: Opening the 5G Radio Interface
(Monday, July 13, 2020)
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Formal Property Checking for IP - A Case Study
(Thursday, July 9, 2020)
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Why VAD and what solution to choose?
(Monday, July 6, 2020)
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Why a True Hardware PUF is more Reliable as RoT
(Thursday, July 2, 2020)
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Antenna Effect in 16nm Technology Node
(Monday, June 29, 2020)
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Analog and Power Management Trends in ASIC and SoC Designs
(Monday, June 29, 2020)
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Where Innovation Is Happening in Geolocation. Part 1: Signal Processing
(Thursday, June 25, 2020)
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SamurAI: a 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to- Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency
(Wednesday, June 24, 2020)
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GRSCRUB: FPGA Configuration Supervisor
(Monday, June 15, 2020)
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A guide to accelerating applications with just-right RISC-V custom instructions
(Monday, June 8, 2020)
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Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
(Monday, June 8, 2020)
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Breaking new energy efficiency records with advanced power management platform
(Monday, June 8, 2020)
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How to Verify Complex RISC-V-based Designs
(Monday, June 1, 2020)
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Time-Domain Analog Design: Why and How
(Monday, June 1, 2020)
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Accelerating 5G virtual RAN deployment
(Friday, May 29, 2020)
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Why Do We Need SERDES?
(Monday, May 25, 2020)
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RoT: The Foundation of Security
(Monday, May 18, 2020)
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Reduce ATPG Simulation Failure Debug Time by Understanding and Editing SPF
(Monday, May 11, 2020)
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5 Tips for Creating a Custom ASIC
(Tuesday, May 5, 2020)
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Build Trust in Silicon: A Myth or a Reality?
(Monday, May 4, 2020)
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Automating C test cases for embedded system verification
(Wednesday, April 29, 2020)
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Why Software is Critical for AI Inference Accelerators
(Wednesday, April 29, 2020)
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Methodology to reduce Run Time of Timing/Functional Eco
(Monday, April 27, 2020)
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Embedded Software Unit Testing with Ceedling
(Tuesday, April 14, 2020)
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The Thriving Silicon IP Business
(Monday, April 6, 2020)
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SRAM PUF: A Closer Look at the Most Reliable and Most Secure PUF
(Monday, April 6, 2020)
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NeoPUF, A Reliable and Non-traceable Quantum Tunneling PUF
(Tuesday, March 31, 2020)
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Understanding Physical Unclonable Function (PUF)
(Monday, March 23, 2020)
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Shift Power Reduction Methods and Effectiveness for Testability in ASIC
(Monday, March 16, 2020)
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Improving performance and security in IoT wearables
(Thursday, March 12, 2020)
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Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
(Monday, March 9, 2020)
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Strategy To Fix Register-to-Register Timing For large Feedthrough Blocks Having Limited Internal Pipelines
(Thursday, March 5, 2020)
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Testing Embedded MRAM IP for SoCs
(Monday, March 2, 2020)
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SRAM PUF is Increasingly Vulnerable
(Wednesday, February 19, 2020)
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Layout versus Schematic (LVS) Debug
(Monday, February 10, 2020)
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Choosing the Right IP for Die-to-Die Connectivity
(Monday, February 3, 2020)
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Interface Timing Challenges and Solutions at Block Level
(Monday, January 27, 2020)
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Setup Margin Aware Quick Hold Fixing
(Monday, January 13, 2020)
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