Blogs
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Highest Performance Xilinx UltraScale-based Prototypes
(Monday, June 15, 2015)
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DAC Keynote: Moore's Law Isn't Dead
(Wednesday, June 10, 2015)
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Predictions about EDA and IP at #52DAC
(Wednesday, June 10, 2015)
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An update on MIPS tools and OS support from Imagination
(Tuesday, June 9, 2015)
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DAC 2015, San Francisco: Must-See Verification Sessions
(Tuesday, June 9, 2015)
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Go to market months faster with Hybrid IP Prototyping (HIP) and USB 3.1 Shipping from its Creator
(Monday, June 8, 2015)
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JEDEC UFS Cheat Sheet
(Monday, June 8, 2015)
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Performance Advantages of Synopsys VIP
(Friday, June 5, 2015)
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IoT Needs New MEMS Approaches
(Thursday, June 4, 2015)
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Cash-Less Intel
(Wednesday, June 3, 2015)
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Why is Intel going inside Altera for Servers?
(Wednesday, June 3, 2015)
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Benefits of MIPI Soundwire
(Wednesday, June 3, 2015)
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On stage with Sir Hossein Yassaie, Facebook, Texas Instruments, Ikanos and Altair at the 2015 Imagination Summit in Santa Clara
(Monday, June 1, 2015)
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MIPI MPHY Cheat Sheet
(Monday, June 1, 2015)
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Xilinx UltraScale VU440 Integrated Design Implementation and DebugXilinx UltraScale VU440 Integrated Design Implementation and Debug
(Monday, June 1, 2015)
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Embedded Vision Ripe for Growth, Rife with Challenges
(Monday, June 1, 2015)
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Configuring Memory VIPs
(Monday, June 1, 2015)
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"Cook's Law" supersedes "Moore's Law"-its impact on Apple, Samsung, TSMC & Intel
(Friday, May 29, 2015)
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Scale & Scalability -- The Keys to True FPGA-Based Verification
(Friday, May 29, 2015)
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Can You Trust a DR-Check Without a DR-Spec?
(Thursday, May 28, 2015)
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Memory VIP Challenges
(Thursday, May 28, 2015)
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How Random is Random? Part 5 - TRNGs - Detecting Patterns
(Thursday, May 28, 2015)
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Three Steps for USB Application Success - Design, Verify, Certify
(Thursday, May 28, 2015)
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Why does Apple do business with Samsung?
(Wednesday, May 27, 2015)
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SoC Debug Made Easy!
(Wednesday, May 27, 2015)
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CEVA DSPs and the Tale of Two Chip Underdogs from China
(Tuesday, May 26, 2015)
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It's Time to Stop Kicking the EDA Dog
(Monday, May 25, 2015)
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How to Push Mobile to Use PCI Express?
(Monday, May 25, 2015)
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Maximizing Debug Visibility in Xilinx UltraScale FPGA-Based Prototypes
(Monday, May 25, 2015)
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How to Design to the "Always-on" IoT Imperative
(Friday, May 22, 2015)
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HDCP 2.2: Locality Check, SKE and Authentication with Repeaters
(Friday, May 22, 2015)
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Low Power, Phones, Tablets and PCIe, Oh My!
(Friday, May 22, 2015)
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Show report: Embedded Vision Summit bigger than ever
(Thursday, May 21, 2015)
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USB3.1 Device DUT: 6 BiGGEST Verification Challenges
(Thursday, May 21, 2015)
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How Random is Random? Part 4 - TRNGs - Endless Methods of Attacks
(Thursday, May 21, 2015)
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MIPI Soundwire: Digital Audio Streams and Channels
(Wednesday, May 20, 2015)
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Intel-Altera Back On says New York Post
(Monday, May 18, 2015)
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FD-SOI the Synapse Way
(Monday, May 18, 2015)
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How Sidense Sees The Smart Connected Universe
(Monday, May 18, 2015)
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Intel and eASIC: Marriage or Just Good Friends?
(Friday, May 15, 2015)
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ASMC 2015: GlobalFoundries 22nm SOI plans and more!
(Friday, May 15, 2015)
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HDCP 2.2: Authentication and Key Exchange (AKE)
(Friday, May 15, 2015)
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UVM Sequences Tutorial
(Wednesday, May 13, 2015)
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How Random is Random? Part 3: TRNG Attacks - When It's No Secret
(Wednesday, May 13, 2015)
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AMBA System Monitor, Scoreboarding and Beyond
(Tuesday, May 12, 2015)
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Is Low Power a Challenge? ICE-Grain Answers the Challenge
(Tuesday, May 12, 2015)
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Indago Protocol Debug and IP Verification
(Monday, May 11, 2015)
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Dynamic Power Estimation Hits Limits of SoC Designs
(Monday, May 11, 2015)
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Flying High with Verification Standard for Design Reliability
(Monday, May 11, 2015)
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Automotive vision processing moving into the camera
(Monday, May 11, 2015)
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