Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (58)
arrow Embedded Memories (996)
arrow I/O Library (1030)
arrow PLL (1747)
arrow Standard cell (756)
58 IP
1
200.0
VDPU (Vector Data Processing Unit)
- The Dnotitia VDPU is a scalable IP core specifically designed to accelerate vector database operations. - It is a comprehensive solution that inclu...
2
10.0
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating point (FP) components th...
3
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
4
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
5
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
6
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
7
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
8
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
9
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
10
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
11
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
12
0.0
Half Precision IEEE-754R complete FPU for graphics processing
This block may be used to convert and existing single register stage into a stallable pipeline stage. It can also be used with synchronous RAM blocks...
13
0.0
Tangent
Fast and low-power tangent function...
14
0.0
Tangent (Hyperbolic)
Fast and low-power hyperbolic tangent function, also suitable for use as an activation function...
15
0.0
Gaussian Error Linear Unit (GELU)
This highly accelerated function implements the Gaussian Error Linear Unit (GELU) activation function that is popular in transformers. This function i...
16
0.0
Adder - Subtractor
Adder-subtractor for AI...
17
0.0
Reciprocal Function
Fast and low power reciprocal function...
18
0.0
Reciprocal of Square Root
Fast and low power reciprocal of the square root function...
19
0.0
IEEE 754 Floating Point Coprocessor
The A2F3 is a fully synthesizable module implemented in Verilog RTL. It is a co-processor unit providing floating-point computation compliant with th...
20
0.0
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The b...
21
0.0
Zero fall-through synchronous FIFO
Fully synchronous FIFO with zero fall-through such that when empty the FIFO behaves like a single stage register....
22
0.0
Sigmoid activation function
This fast and low-power sigmoid function is a great improvement over simple activation functions...
23
0.0
SiLU-SwiGLU Activation Function
This fast and low-power SiLU function is a great improvement over simple activation functions, can be used alone or together with a multiplier to crea...
24
0.0
Sine
Fast and low-power sine function...
25
0.0
Sine - Cosine
Fast and low-power selectable sine or cosine function...
26
0.0
Single- and double-precision IEEE-754 floating-point unit
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu...
27
0.0
Mish Activation Function
This fast and low-power mish function is a great improvement over simple activation functions...
28
0.0
Divider
Divider for AI...
29
0.0
Floating point adder
Floating point adder...
30
0.0
Floating point MAC
Floating point MAC...
31
0.0
Floating point multiplier
Floating point multiplier...
32
0.0
Floating Point Multiply-Accumulate
Floating Point Multiply-Accumulate unit, highly accelerated, for standalone use or integration into higher-order AI functions...
33
0.0
SoftMax Accelerator
Cassia.ai SoftMax functions are incredibly fast and low power, and may be piplined as needed. Our SoftMax functions are built to order to meet each cu...
34
0.0
Log (Base K)
Base-K Log generator, highly accelerated, for standalone use or integration into higher-order functions...
35
0.0
Logarithm (Base 10) - Log10
Base-10 Log generator, highly accelerated, for standalone use or integration into higher-order functions...
36
0.0
Logarithm (Base 2) - Log2
Base-2 Log generator, highly accelerated, for standalone use or integration into higher-order functions...
37
0.0
Logarithm (natural)
Natural Log generator, highly accelerated, for standalone use or integration into higher-order functions...
38
0.0
Color Camera Sensor Bayer Decoder
Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern. Bayer filter in front of the sensor embeds color i...
39
0.0
DolphinWare Arithmetic Components Ips
Dolphin Technology provides DolphinWare Arithmetic Components IPs, consist of Math Operators and Converters....
40
0.0
DolphinWare Control Logic Ips
Dolphin Technology provides DolphinWare Control Logic IPs, consist of Arbiter and FIFO....
41
0.0
DolphinWare Data Integrity Ips
Dolphin Technology provides DolphinWare Data Integrity IPs, consist of Encoders, Decoders and Error Correction....
42
0.0
DolphinWare Logic Components Ips
Dolphin Technology provides DolphinWare Logic Components IPs, consist of Counters, Registers and MUXs....
43
0.0
DolphinWare Verification Ips
Dolphin Technology provides DolphinWare Verification IPs (VIPs), consist of AXI4, APB, SD4.0/UHS-II, I2C, I3C, I2S....
44
0.0
Cosine
Fast and low-power cosine function...
45
0.0
Square Root
Square Root function...
46
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
47
0.0
Asynchronous FIFO with flags and depth counter
...
48
0.0
Stallable 1toN Expansion Pipeline Register
This block is used as a width expander as part of a processing pipeline. It may receive multiple(N) input words, concatenate them and present them fo...
49
0.0
Stallable Nto1 Contraction Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the rat...
50
0.0
Stallable Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully comp...