Design & Reuse
Catalog of SIP Cores
System on Chip design resources
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4587 IP
951
1.0
UMC L90G 90nm Spread Spectrum PLL - 180MHz-900MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
952
1.0
UMC L90G 90nm Spread Spectrum PLL - 360MHz-1800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
953
1.0
UMC L90G 90nm Spread Spectrum PLL - 90MHz-450MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
954
1.0
UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
955
1.0
UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
956
1.0
UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
957
1.0
UMC L90GOD 90nm Deskew PLL - 125MHz-625MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
958
1.0
UMC L90GOD 90nm Deskew PLL - 250MHz-1250MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
959
1.0
UMC L90GOD 90nm Deskew PLL - 500MHz-2500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
960
1.0
UMC L90GOD 90nm Spread Spectrum PLL - 125MHz-625MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
961
1.0
UMC L90GOD 90nm Spread Spectrum PLL - 250MHz-1250MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
962
1.0
UMC L90GOD 90nm Spread Spectrum PLL - 500MHz-2500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
963
1.0
UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
964
1.0
UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
965
1.0
UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
966
1.0
UMC L90SP 90nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
967
1.0
UMC L90SP 90nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
968
1.0
UMC L90SP 90nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
969
1.0
UMC L90SP 90nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
970
1.0
UMC L90SP 90nm Spread Spectrum PLL - 240MHz-1200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
971
1.0
UMC L90SP 90nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
972
1.0
SMIC 0.11um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...
973
1.0
SMIC 0.11um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 6T HVT High-Density Standard Cell Library...
974
1.0
SMIC 0.11um 6 track High Density Standard Cell Library - LVT,1.2v operating voltage
SMIC 0.11um 6T LVT High-Density Standard Cell Library...
975
1.0
SMIC 0.11um 6 track High Density Standard Cell Library - RVT,1.2v operating voltage
SMIC 0.11um 6T RVT High-Density Standard Cell Library...
976
1.0
SMIC 0.11um 7 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 7T HVT High-Density Standard Cell Library...
977
1.0
SMIC 0.11um 7 track High Density Standard Cell Library - LVT,1.2v operating voltage
SMIC 0.11um 7T LVT High-Density Standard Cell Library...
978
1.0
SMIC 0.11um 7 track High Density Standard Cell Library - RVT,1.2v operating voltage
SMIC 0.11um 7T RVT High-Density Standard Cell Library...
979
1.0
SMIC 0.11um 9 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 9 track Standard Cell Library - HVT,1.2v operating voltage...
980
1.0
SMIC 0.11um 9 track High Density Standard Cell Library - LVT,1.2v operating voltageSMIC 0.11um 9 track High Density Standard Cell Library - LVT,1.2v operating voltage
SMIC 0.11um 9 track Standard Cell Library - LVT,1.2v operating voltage...
981
1.0
SMIC 0.11um 9 track High Density Standard Cell Library - RVT, 1.2v operating voltage
SMIC 0.11um 9T RVT High-Density Standard Cell Library...
982
1.0
SMIC 0.11um Power Management Kit,1.2v operating voltage
SMIC 0.11um Power Management Kit Library...
983
1.0
SMIC 0.13um 1.2v / 3.3v Audio PLL
This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports both 256X and 384X oversamplin...
984
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...
985
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...
986
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...
987
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(...
988
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for generating system clock. It contains a PFD, Charge pump, 3rd order loop filter, a 1-64 input clock d...
989
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for generating system clock. High speed VCO can run from 250MHz to 500MHz. By setting DM [5:0] and DN [7...
990
1.0
SMIC 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...
991
1.0
SMIC 0.13um 1.2v FN-PLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 500MHz. It contains a 1-64 in...
992
1.0
SMIC 0.13um 1.2V/2.5V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
993
1.0
SMIC 0.13um 1.2V/3.3V ANALOGIO_05 IO Library
VeriSilicon SMIC 0.13um 1.2V/3.3V ANALOGIO_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
994
1.0
SMIC 0.13um 1.2v/3.3v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 100MHz to 300MHz (If the analog power drops...
995
1.0
SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO
VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporati...
996
1.0
SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or the input clock. It supports 256*fs clock output, where fs is...
997
1.0
SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. The reference clock is 13.5MHz crystal or the input clock. It supports 256*fs clock output and 384*fs...
998
1.0
SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. The reference clock is either 12MHz crystal or the input clock. It supports 256*fs and 128*fs clock o...
999
1.0
SMIC 0.13um 1.2v/3.3v PLL
This PLL is designed for audio clock generation. It can support 8.192MHz/10MHz/12MHz/12.288MHz/13MHz/13.5MHz/19.2MHz/21.25MHz/24MHz/26MHz/38.85MHz as ...
1000
1.0
SMIC 0.13um 1.2v/3.3v PLL Specification
This PLL is designed for audio clock generation. The reference clock is either 12MHz crystal or the input clock. It supports 256*fs clock output, wher...