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1551

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library...

1552

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library...

1553

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library...

1554

0.118

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....

1555

0.118

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....

1556

0.118

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy....

1557

0.118

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler.

UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler....

1558

0.118

UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.

UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler....

1559

0.118

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.

UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....

1560

0.118

UMC 40nm Low Power Process , Two Port Register File with dual power rail

UMC 40nm Low Power Process , Two Port Register File with dual power rail...

1561

0.118

UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail

UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail...

1562

0.118

UMC 40nm Low Power Process One Port Register File wit 213 cell

UMC 40nm Low Power Process One Port Register File wit 213 cell...

1563

0.118

UMC 40nm Low Power Process One Port Register File with 213 cell

UMC 40nm Low Power Process One Port Register File with 213 cell...

1564

0.118

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell...

1565

0.118

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating...

1566

0.118

UMC 40nm Low Power Process Single-Port SRAM for dual power rail

UMC 40nm Low Power Process Single-Port SRAM for dual power rail...

1567

0.118

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...

1568

0.118

UMC 40nm Low Power Process SP-SRAM with 213 bit cell

UMC 40nm Low Power Process SP-SRAM with 213 bit cell...

1569

0.118

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral....

1570

0.118

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral....

1571

0.118

UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail

UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail...

1572

0.118

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1573

0.118

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1574

0.118

UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

1575

0.118

UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode

UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode...

1576

0.118

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...

1577

0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...

1578

0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...

1579

0.118

UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral

UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral...

1580

0.118

UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral

UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral...

1581

0.118

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT

UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT...

1582

0.118

UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT

UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT...

1583

0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...

1584

0.118

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral

UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...

1585

0.118

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler

UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...

1586

0.118

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler

UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...

1587

0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...

1588

0.118

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT

UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT...

1589

0.118

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 40nm LP Logic Process Ultra High Speed One-Port Register File...

1590

0.118

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT

UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT...

1591

0.118

UMC 40nm LP process standard synchronous high density TCAM memory compiler.

UMC 40nm LP process standard synchronous high density TCAM memory compiler....

1592

0.118

UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.

UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy....

1593

0.118

UMC 40nm LP with power gating & peri-HVT 1PRF

UMC 40nm LP with power gating & peri-HVT 1PRF...

1594

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library...

1595

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T GENERIC CORE Cell Library...

1596

0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1597

0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library...

1598

0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T GENERIC CORE Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T GENERIC CORE Cell Library...

1599

0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1600

0.118

UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library

UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library...

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