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2743 IP
1701
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
1702
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
1703
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
1704
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell....
1705
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
1706
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....
1707
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...
1708
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1709
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
1710
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...
1711
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...
1712
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1713
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
1714
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
1715
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
1716
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....
1717
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
1718
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...
1719
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1720
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....
1721
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
1722
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...
1723
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
1724
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....
1725
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
1726
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
1727
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
1728
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
1729
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
1730
0.118
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias...
1731
0.118
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias...
1732
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
1733
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
1734
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...
1735
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....
1736
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
1737
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
1738
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
1739
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell....
1740
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...
1741
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....
1742
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
1743
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
1744
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
1745
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1746
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1747
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1748
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
1749
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias...
1750
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
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