Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (58)
arrow Embedded Memories (996)
arrow I/O Library (1030)
arrow PLL (1747)
arrow Standard cell (756)
4587 IP
2051
0.118
General Purpose Multi-Voltage IO IP, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process Multi-Voltage BOAC IO Cell Library (with customized PU/PD function)....
2052
0.118
General Purpose Multi-Voltage IO IP, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Multi-Voltage floating N-well BOAC IO Cell Library....
2053
0.118
General Purpose Multi-Voltage IO IP, With Power-on Control features, UMC 0.11um eFlash process
UMC 0.11um eFlash/EE2PROM Process BOAC Multi-Voltage IO with Power-on Tri-state/Low Function....
2054
0.118
Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process True 1.8V Metal-programmable IO (MPIO) Cell Library....
2055
0.118
Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process Multi-Voltage metal programmable IO Cell Library....
2056
0.118
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process...
2057
0.118
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process...
2058
0.118
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process...
2059
0.118
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process...
2060
0.118
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user...
2061
0.118
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40...
2062
0.118
Single Port SRAM Compiler IP, UMC 0.11um EEPROM process
UMC 0.11um EE2PROM/LL 1.5V high density Single Port SRAM compiler....
2063
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler....
2064
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler....
2065
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler....
2066
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler....
2067
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler....
2068
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Single Port SRAM memory compiler....
2069
0.118
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler....
2070
0.118
Single Port SRAM Compiler IP, UMC 0.35um SP process
UMC 0.35um Logic process synchronous high speed Single Port SRAM memory compiler....
2071
0.118
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process.
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process....
2072
0.118
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)...
2073
0.118
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler....
2074
0.118
HJTC 0.11um uLL/pFlash Single Port SRAM compiler
HJTC 0.11um uLL/pFlash Single Port SRAM compiler...
2075
0.118
HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
HJTC 0.11um uLL/pFlash via1 ROM memory compiler....
2076
0.118
HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM
HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM...
2077
0.118
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
2078
0.118
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
2079
0.118
PLL (All Digital, Spread Spectrum) IP, Input: clock range:10MHz - 1280MHz, Output: 15.625MHz - 2GHz, Spreading depth: -10%(max), Spreading Freq: 20KHz to 300KHz, UMC 0.11um HS/AE process
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
2080
0.118
PLL (De-Skew) IP, Input: 15MHz - 110MHz, Output: 15MHz - 110MHz, UMC 0.13um HS/FSG process
Input 15M-110MHz, output 15M-110MHz, De-skew PLL with 0.9V~1.32V power supply range, UMC 0.13um HS/FSG Logic process....
2081
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, HJTC 0.18um eFlash/G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, HJTC 0.18 eFlash process....
2082
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....
2083
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....
2084
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process....
2085
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL, UMC 0.11um HS/AE Logic process, It has lock detector function....
2086
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process
Input 10M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um SP/FSG Logic process....
2087
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 55nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 55nm SP Low-K Logic process....
2088
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process....
2089
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
2090
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
2091
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
2092
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Input 10M-500MHz, Output 31.25M-500MHz, frequency synthesizer PLL, UMC 65nm SP/RVT Low-K process....
2093
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process....
2094
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0L, but Poly Density E...
2095
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz, Output: 40MHz - 60MHz, HJTC 0.18um eFlash/G2 process
Input 10MHz, output 40M-60MHz, frequency synthesizable PLL, HJTC 0.18um eFlash process....
2096
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process....
2097
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process....
2098
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um SP/FSG process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process....
2099
0.118
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
Input 12M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process....
2100
0.118
PLL (Frequency Synthesizer) IP, Input: 12MHz - 200MHz, Output: 250MHz - 500MHz, UMC 40nm LP process
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250MHz and 500MHz, UMC 40nm LP/RVT Logic process....