Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Arithmetic & Mathematic (46)
arrow Embedded Memories (994)
arrow I/O Library (1032)
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2828 IP
2751
0.0
TSMC embedded flash controller
The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros....
2752
0.0
TSMC N3P 1.2V High-Speed Test IO MS add-on
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...
2753
0.0
TSMC N3P 1.2V IO Platform supporting cells with Additional Features
The AI and HPC industries are advancing toward chiplet-based designs to achieve superior performance, as traditional monolithic SoCs face scaling chal...
2754
0.0
TSMC N3P 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2755
0.0
TSMC N3P Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2756
0.0
TSMC N3P Source Sync 3DIO PHY
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2757
0.0
TSMC N5 Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2758
0.0
PSRAM/SD3.0/EMMC5.1 IO in SMIC 28HKD 0.9/2.5V, upto 600Mbps
...
2759
0.0
SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...
2760
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
2761
0.0
Asynchronous FIFO with flags and depth counter
...
2762
0.0
Stallable 1toN Expansion Pipeline Register
This block is used as a width expander as part of a processing pipeline. It may receive multiple(N) input words, concatenate them and present them fo...
2763
0.0
Stallable Nto1 Contraction Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the rat...
2764
0.0
Stallable Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully comp...
2765
0.0
Standard Cell Libraries, GF 55nm
Silvaco’s Standard Cell libraries deliver thousands of highly optimized cells with each one being optimized for power, area, speed, routing, and yield...
2766
0.0
Standard Cell Library Low Voltage Operation 0.45 V
Silvaco’s low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance SoC designs. A...
2767
0.0
LTE Cat 1bis RF, Modem and Protocol Stack IP
This LTE Cat 1bis Cellular IoT IP delivers low-power, global connectivity for cost-sensitive IoT and M2M devices requiring higher throughput than LTE-...
2768
0.0
OTP IP
Zhuhai Chuangfeixin (CFX) offers two proprietary OTP technologies and respective silicon IPs：One is Anti-fuse, the other is floating gate. CFX OTP ...
2769
0.0
OTP One Time Programmable IP HHGrace 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2770
0.0
OTP One Time Programmable IP HHGrace 55LP
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2771
0.0
OTP One Time Programmable IP HHGrace 90BCD
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2772
0.0
OTP One Time Programmable IP HLMC 55CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2773
0.0
OTP One Time Programmable IP Nexchip 110HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2774
0.0
OTP One Time Programmable IP Nexchip 110LP2
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2775
0.0
OTP One Time Programmable IP Nexchip 55HV_6V
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2776
0.0
OTP One Time Programmable IP Samsung 90CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2777
0.0
OTP One Time Programmable IP SIL130HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2778
0.0
OTP One Time Programmable IP SIL180
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2779
0.0
OTP One Time Programmable IP Silterra 160HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2780
0.0
OTP One Time Programmable IP SMIC 153nm
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2781
0.0
OTP One Time Programmable IP SMIC 28HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2782
0.0
OTP One Time Programmable IP SMIC 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2783
0.0
OTP One Time Programmable IP SMIC130
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2784
0.0
OTP One Time Programmable IP XMC 55LL
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
2785
0.0
Dual Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Dual Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
2786
0.0
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm FDX-PLUS CMOS...
2787
0.0
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Low Leakage. Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm F...
2788
0.0
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range up to 80 k...
2789
0.0
SUB-LVDS TX PHY
The InPsytech Low-Voltage Differential Signaling (LVDS) is a well-established high-speed interface known for its excellent combination of fast data ra...
2790
0.0
subLVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 14...
2791
0.0
Queue Structure
The A2Q implements hardware queues for use as FIFOs and LIFOs for inter-process communications, especially in real-time applications. They can be us...
2792
0.0
Bulk 40ULP single port SRAM Compiler - ultra low power, low power retention mode
Silicon proven, qualified and in high volume production. Single Port compiler offers the lowest retention power on the market....
2793
0.0
Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
Low Leakage. Mobile Semiconductor's Bulk 40 ULP BULKSRAM memory compiler generates memory instances using the premier low power 40nm process.. Each ul...
2794
0.0
LVDS IO in SMIC 28HKC+, upto 1.6Gbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
2795
0.0
LVDS IO in SMIC 40NLL, upto 800Mbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
2796
0.0
LVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit...
2797
0.0
LVDS Receiver
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The d...
2798
0.0
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is ...
2799
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
2800
0.0
LVDS Transmitter
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and high data rates. The...