Design & Reuse
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2793 IP
2751
0.0
TSMC embedded flash controller
The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros....
2752
0.0
TSMC N3P 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2753
0.0
TSMC N3P Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2754
0.0
TSMC N3P Source Sync 3DIO PHY
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2755
0.0
TSMC N5 Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2756
0.0
PSRAM/SD3.0/EMMC5.1 IO in SMIC 28HKD 0.9/2.5V, upto 600Mbps
...
2757
0.0
SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...
2758
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
2759
0.0
Asynchronous FIFO with flags and depth counter
...
2760
0.0
Stallable 1toN Expansion Pipeline Register
This block is used as a width expander as part of a processing pipeline. It may receive multiple(N) input words, concatenate them and present them fo...
2761
0.0
Stallable Nto1 Contraction Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the rat...
2762
0.0
Stallable Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully comp...
2763
0.0
Standard Cell Library, 0.45 V, 3nm, 7.5-Track
Silvaco’s low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance SoC designs. A...
2764
0.0
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm FDX-PLUS CMOS...
2765
0.0
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Low Leakage. Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates Dual Port Register File instances using the GLOBALFOUNDRIES 22nm F...
2766
0.0
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range up to 80 k...
2767
0.0
SUB-LVDS TX PHY
The InPsytech Low-Voltage Differential Signaling (LVDS) is a well-established high-speed interface known for its excellent combination of fast data ra...
2768
0.0
subLVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 14...
2769
0.0
Queue Structure
The A2Q implements hardware queues for use as FIFOs and LIFOs for inter-process communications, especially in real-time applications. They can be us...
2770
0.0
Bulk 40ULP single port SRAM Compiler - ultra low power, low power retention mode
Silicon proven, qualified and in high volume production. Single Port compiler offers the lowest retention power on the market....
2771
0.0
Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
Low Leakage. Mobile Semiconductor's Bulk 40 ULP BULKSRAM memory compiler generates memory instances using the premier low power 40nm process.. Each ul...
2772
0.0
LVDS I/O Buffer 40/28/22/16/7nm
The LVDS I/O has driver and receiver of TSMC 7, 16, 22, 28, 40nm and Samsung 14nm process. ● Support LVDS specification is TIA/EIA-644-A. ● LVDS dri...
2773
0.0
LVDS IO in SMIC 28HKC+, upto 1.6Gbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
2774
0.0
LVDS IO in SMIC 40NLL, upto 800Mbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
2775
0.0
LVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit...
2776
0.0
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is ...
2777
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
2778
0.0
LVDS Tx and OpenLDI Tx (Automotive IP)
InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...
2779
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
2780
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
2781
0.0
LVDS TX+ (Transmitter) in UMC 40LP
The MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequenc...
2782
0.0
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be eas...
2783
0.0
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS transmitter. This IP consists of 20-lane (4 x 4D1C) LVDS drivers and supports up to 1.5Gbps data rate. In LVDS mode, both...
2784
0.0
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and ...
2785
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
2786
0.0
Two port register file (1R1W) with low power retention mode
Low Leakage. Mobile Semiconductor's Bulk 22 ULL Register file memory compiler generates dual port Register File instances using the Bulk 22ULL proces...
2787
0.0
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range...
2788
0.0
Two Port Register File compiler - Memory optimized for high density and low power optimized - compiler range up to 40 k
Foundry sponsored - Two Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power optimized - compiler range up ...
2789
0.0
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....
2790
0.0
1x32 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 0.18um SiGe Bi...
2791
0.0
1x64 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- Mixed-Signal ...
2792
0.0
Synopsys High-Speed Test IO in TSMC N3P
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...
2793
0.0
Synthesizable 3DIO IP for Flexible Physical Implementation
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...