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1723 IP
301
1.0
High-Performance CLKPLL with 1 VCO from 10GHz to 12GHz - GlobalFoundries 40nm
High-Performance CLKPLL with 1 VCO from 10GHz to 12GHz - GlobalFoundries 40nm...
302
1.0
High-Performance RFPLL with 3 VCOs from 7GHz to 12GHz - GlobalFoundries 40nm
High-Performance RFPLL with 3 VCOs from 7GHz to 12GHz - GlobalFoundries 40nm...
303
1.0
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) + GSM VCO (Fmid=7.2GHz) - GlobalFoundries 55nm
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) + GSM VCO (Fmid=7.2GHz) - GlobalFoundries 55nm...
304
1.0
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) + GSM VCO (Fmid=7.2GHz) - STMicroelectronics 65nm
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) + GSM VCO (Fmid=7.2GHz) - STMicroelectronics 65nm...
305
1.0
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) - GlobalFoundries 55nm
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) - GlobalFoundries 55nm...
306
1.0
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) - STMicroelectronics 65nm
High-Performance RFPLL with Wide-Tuning VCO (Fmid=6GHz) - STMicroelectronics 65nm...
307
1.0
SilTerra 0.18um 1.8V APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 600MHz. It contains a 1-64 in...
308
1.0
SIMC 65nm LL 2.5v Audio PLL
This PLL is designed for audio clock generation. The reference clock is 12MHz, 13.5MHz or 19.2MHz, which can be either from the crystal OSC or from in...
309
1.0
PLL
INNOSILICON™ PLL IP is a high-speed, low-jitter frequency synthesizer, developed to reduce time-to-market, risk, and design cost. It can generate a st...
310
1.0
PLL - SMIC 55nm Eflash
...
311
1.0
PLL - SMIC 55nm Eflash
...
312
1.0
PLL - SMIC 55nm Eflash
...
313
1.0
PLL - SMIC 55nm Eflash
...
314
1.0
PLL - SMIC130nm Eflash
...
315
1.0
PLL for TSMC 130nm LP
The OT3122t130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC 0.13µ LP or ...
316
1.0
PLL Fractional-N. Extreme low jitter (1pS RMS)
PLL Fractional-N. Extreme low jitter (1pS RMS)...
317
1.0
GLOBALFOUNDRIES 0.11um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...
318
1.0
GLOBALFOUNDRIES 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-6...
319
1.0
GLOBALFOUNDRIES 0.13um 1.2V POR
Present Power on Reset generates system reset signal (RESET and RESETN) when 1.2V power (POR_VDD) rises to a specific level, i.e., Vtr....
320
1.0
GLOBALFOUNDRIES 22nm FDSOI 1.8v/0.8v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [5:0] ...
321
1.0
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz....
322
1.0
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v PLL
...
323
1.0
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v PLL
...
324
1.0
GLOBALFOUNDRIES 28nm SLP 2.5v/1.0v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz.By setting DM [5:0] a...
325
1.0
GLOBALFOUNDRIES 40nm Low Power 1.1v/2.5v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 300MHz to 900MHz. By setting DM[3:0], D...
326
1.0
Ultra-low power and low jitter PLL
...
327
1.0
UMC 0.18um 3.3v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run at about 100MHz. By setting different values...
328
1.0
UMC L130HS 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
329
1.0
UMC L130HS 130nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
330
1.0
UMC L130HS 130nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
331
1.0
UMC L130HS 130nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
332
1.0
UMC L130HS 130nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
333
1.0
UMC L130HS 130nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
334
1.0
UMC L130HS 130nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
335
1.0
UMC L130HS 130nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
336
1.0
UMC L130HS 130nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
337
1.0
UMC L130LL 130nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
338
1.0
UMC L130LL 130nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
339
1.0
UMC L130LL 130nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
340
1.0
UMC L130LL 130nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
341
1.0
UMC L130LL 130nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
342
1.0
UMC L130LL 130nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
343
1.0
UMC L130LL 130nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
344
1.0
UMC L130LL 130nm Spread Spectrum PLL - 30MHz-150MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
345
1.0
UMC L130LL 130nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
346
1.0
UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
347
1.0
UMC L130SP 130nm Clock Generator PLL - 236MHz-1180MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
348
1.0
UMC L130SP 130nm Clock Generator PLL - 59MHz-295MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
349
1.0
UMC L130SP 130nm Deskew PLL - 118MHz-590MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
350
1.0
UMC L130SP 130nm Deskew PLL - 236MHz-1180MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
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