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97 IP
1
100.0
Adaptive Clock Generation Module for DVFS and Droop Response
The Movellus™ Aeonic Generate AWM3 high-performance clock generation IP product is part of the Aeonic digital IP product family. Designed for Droop Mi...
2
100.0
Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)
Widely programmable frequency synthesizers with industry leading jitter performance....
3
100.0
TSMC GF Intel Low Phase Noise, High-performance Digital LC PLL
Fractional-N LC based frequency synthesizer with digital loop filter for high performance clock generation applications. See our features list for mor...
4
100.0
TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
High-bandwidth, De-Skew Frequency Synthesizer for minimizing clock tree timing uncertainty. See our features list for more details....
5
100.0
TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
Widely programmable fractional-N delta sigma frequency synthesizer with industry leading jitter performance. See our features list for more details....
6
100.0
TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL
Widely programmable integer-N frequency synthesizer with industry leading jitter performance and flexible power options. See our features list for mor...
7
100.0
TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL
Low-bandwidth, Ultra-Fast-Lock Frequency Synthesizer, capable to operate with a very low reference frequencies (32kHz - 33kHz). See our features list ...
8
100.0
TSMC Samsung GF Intel CML mux - on-chip clock buffer
Distribute high-performance clock across your chip with reduced supply-noise coupling. See our features list for more details....
9
10.0
Differential Clock Receiver - TSMC CLN2P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
10
10.0
Differential Clock Receiver - TSMC CLN3A
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
11
10.0
Differential Clock Receiver - TSMC CLN3E
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
12
10.0
Differential Clock Receiver to CML - TSMC CLN2P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
13
10.0
Differential Clock Receiver to CML - TSMC CLN3A
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
14
10.0
Differential Clock Receiver to CML - TSMC CLN3E
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
15
10.0
Differential Clock Receiver to CML - TSMC CLN6FF
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
16
10.0
Differential Clock Reciever - TSMC CLN3P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
17
10.0
Differential Clock Reciever to CML - TSMC CLN3P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
18
10.0
ULP 10MHz Clock Generator - GlobalFoundries 22FDX
Ultra-low power 10 MHz clock multiplier from a low frequency reference....
19
10.0
ULV Clock Generator - GlobalFoundries 22FDX
ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip....
20
8.0
General Purpose Fractional-N PLLs
Perceptia’s DeepSub™ pPLL02F is a family of all purpose all digital PLLs featuring low-jitter and compact area suitable for many clocking applications...
21
8.0
Low Voltage, Low Power Fractional-N PLLs
Perceptia’s DeepSub™ pPLL05 is a family of low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and em...
22
8.0
Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
Perceptia’s DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requi...
23
8.0
Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
Perceptia’s DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requi...
24
7.0
Low Voltage, Low Power Fractional-N PLL
Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area. It is suitable for IoT and embedded clo...
25
6.0
Fractional-N PLL for Performance Computing in Samsung 14LPP
Perceptia’s DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requi...
26
6.0
Fractional-N PLL for Performance Computing in Samsung 8LPP
Perceptia’s DeepSub™ pPLL03F is an PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at f...
27
6.0
Fractional-N PLL for Performance Computing in TMSC 16FFC
Perceptia’s DeepSub™ pPLL03F is an all digital PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requi...
28
6.0
Fractional-N PLL for Performance Computing in TSMC N5/N4
Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at fr...
29
6.0
Fractional-N PLL for Performance Computing in TSMC N6/N7
Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at fr...
30
6.0
Fractional-N PLL for Performance Computing in UMC40LP
Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at fr...
31
6.0
Fractional-N PLLs for Performance Computing
Perceptia’s DeepSub™ pPLL03F is a family of all digital PLLs featuring low-jitter and compact area suitable for clocking applications with critical ti...
32
4.0
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals....
33
3.0
Programmable Clock Generator
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs. While six clock output...
34
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
35
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
36
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K X...
37
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01 IP is an auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K XOSC, POR,...
38
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC02ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
39
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC02ANA Analog IP is an auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K ...
40
2.0
16MHz to 64MHz Fractional-N RC Phase-Locked Loop
130GF_PLL_01 is a ring VCO based phase-locked loop frequency with 16-64 MHz CMOS compatible output clock and fine frequency resolution thanks to the e...
41
1.0
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Rel11 and Rel12. CorePL...
42
0.118
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process...
43
0.118
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process...
44
0.118
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process...
45
0.118
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process....
46
0.118
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic...
47
0.118
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm...
48
0.118
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....
49
0.118
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process...
50
0.118
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x005F_x005F_x000D_
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process....