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1704 IP
701
1.0
TSMC CLN80HS 80nm Deskew PLL - 500MHz-2500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
702
1.0
TSMC CLN80HS 80nm Spread Spectrum PLL - 125MHz-625MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
703
1.0
TSMC CLN80HS 80nm Spread Spectrum PLL - 250MHz-1250MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
704
1.0
TSMC CLN80HS 80nm Spread Spectrum PLL - 500MHz-2500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
705
1.0
TSMC CLN90G 90nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
706
1.0
TSMC CLN90G 90nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
707
1.0
TSMC CLN90G 90nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
708
1.0
TSMC CLN90G 90nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
709
1.0
TSMC CLN90G 90nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
710
1.0
TSMC CLN90G 90nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
711
1.0
TSMC CLN90G 90nm General Purpose PLL - 160MHz-800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
712
1.0
TSMC CLN90G 90nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
713
1.0
TSMC CLN90G 90nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
714
1.0
TSMC CLN90G 90nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
715
1.0
TSMC CLN90GOD 90nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
716
1.0
TSMC CLN90GOD 90nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
717
1.0
TSMC CLN90GOD 90nm Clock Generator PLL - 440MHz-2200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
718
1.0
TSMC CLN90GOD 90nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
719
1.0
TSMC CLN90GOD 90nm Deskew PLL - 220MHz-1100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
720
1.0
TSMC CLN90GOD 90nm Deskew PLL - 440MHz-2200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
721
1.0
TSMC CLN90GOD 90nm General Purpose PLL - 220MHz-1100MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
722
1.0
TSMC CLN90GOD 90nm Spread Spectrum PLL - 110MHz-550MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
723
1.0
TSMC CLN90GOD 90nm Spread Spectrum PLL - 220MHz-1100MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
724
1.0
TSMC CLN90GOD 90nm Spread Spectrum PLL - 440MHz-2200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
725
1.0
TSMC CLN90GT 90nm Clock Generator PLL - 125MHz-625MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
726
1.0
TSMC CLN90GT 90nm Clock Generator PLL - 250MHz-1250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
727
1.0
TSMC CLN90GT 90nm Clock Generator PLL - 500MHz-2500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
728
1.0
TSMC CLN90GT 90nm Deskew PLL - 125MHz-625MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
729
1.0
TSMC CLN90GT 90nm Deskew PLL - 250MHz-1250MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
730
1.0
TSMC CLN90GT 90nm Deskew PLL - 500MHz-2500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
731
1.0
TSMC CLN90GT 90nm General Purpose PLL - 250MHz-1250MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
732
1.0
TSMC CLN90GT 90nm Spread Spectrum PLL - 125MHz-625MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
733
1.0
TSMC CLN90GT 90nm Spread Spectrum PLL - 250MHz-1250MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
734
1.0
TSMC CLN90GT 90nm Spread Spectrum PLL - 500MHz-2500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
735
1.0
TSMC CLN90LP 90nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
736
1.0
TSMC CLN90LP 90nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
737
1.0
TSMC CLN90LP 90nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
738
1.0
TSMC CLN90LP 90nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
739
1.0
TSMC CLN90LP 90nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
740
1.0
TSMC CLN90LP 90nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
741
1.0
TSMC CLN90LP 90nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
742
1.0
TSMC CLN90LP 90nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
743
1.0
TSMC CLN90LP 90nm Spread Spectrum PLL - 240MHz-1200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
744
1.0
TSMC CLN90LP 90nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
745
1.0
GSMC RF 0.18um 1.8V APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 300MHz to 600MHz. By setting DM[4:0] and DN...
746
1.0
audio clock Generation, output nine kinds of 256*fs from 12M reference input
This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or input clock. It supports 256*fs clock output, here fs is audi...
747
0.118
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user...
748
0.118
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40...
749
0.118
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process.
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process....
750
0.118
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....