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1705 IP
1251
0.0
UMC L40LP 40nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1252
0.0
UMC L55LP 55nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1253
0.0
UMC L55LP 55nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1254
0.0
UMC L55LP 55nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1255
0.0
UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1256
0.0
UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1257
0.0
UMC L55LP 55nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1258
0.0
UMC L55LP 55nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1259
0.0
UMC L55LP 55nm IoT PLL - 30MHz-300MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
1260
0.0
UMC L55LP 55nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1261
0.0
UMC L55LP 55nm Spread Spectrum PLL - 240MHz-1200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1262
0.0
UMC L55LP 55nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1263
0.0
UMC L55LP 55nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1264
0.0
UMC L55SP 55nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1265
0.0
UMC L55SP 55nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1266
0.0
UMC L65LL 65nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1267
0.0
UMC L65LL 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1268
0.0
UMC L65LP 65nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1269
0.0
UMC L65LP 65nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1270
0.0
UMC L65LP 65nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1271
0.0
UMC L65LP 65nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1272
0.0
UMC L65LP 65nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1273
0.0
UMC L65LP 65nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1274
0.0
UMC L65LP 65nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1275
0.0
UMC L65LP 65nm IoT PLL - 30MHz-300MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
1276
0.0
UMC L65LP 65nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1277
0.0
UMC L65LP 65nm Spread Spectrum PLL - 240MHz-1200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1278
0.0
UMC L65LP 65nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1279
0.0
UMC L65LP 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1280
0.0
UMC L65SP 65nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1281
0.0
UMC L65SP 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1282
0.0
1MHz to 50MHz Fractional-N Phase-Locked Loop
055TSMC_PLL_01 is an integer-N phase-locked loop frequency synthesizer (PLL), which produces stable clock signal in range from 50 to 800 MHz. It works...
1283
0.0
1MHz to 600MHz Phase-Locked Loop
The synthesizer produces stable clock signal in range from 1 to 600MHz. PLL with integer factors of the frequency division is used for synthesis. Ex...
1284
0.0
SMIC40nm Integer-N PLL, 600M-2.4G
This present IP is a self-biased Phase Locked Loop (PLL) circuit, which can cover 600MHz-2.4GHz vco output frequency. It can generate adjustable clock...
1285
0.0
MMWave 80GHz PLL with VCO frequency range 19.00-20.25 GHz
MMWave 80GHz Analog FracN PLL with VCO frequency range 19.00-20.25 GHz, Including Integrated PFD, CP, LPF, VCO...
1286
0.0
Low Power 300-600 MHz programmable PLL
The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply. This PLL has a wide programmable frequency range operation opera...
1287
0.0
Low Power Fractional PLL IP(12/16nm, 22nm, 28nm)
Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz and 3:1 output frequenc...
1288
0.0
Low Power High Speed 1.2GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.2GHz is required to lock to an incoming clock source and produce an output clock available at 40nm....
1289
0.0
Low Power High Speed 1GHz Frac-N PLL IP Core
An ultra-low-power programmable fractional-N at 1GHz phase-locked loop (PLL) for frequency synthesis available at 28nm....
1290
0.0
Low Power PLL for 55nm UMC ULP CMOS
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for UMC 55nm, CM...
1291
0.0
Low PowerHigh Speed 1.6GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.6GHz is required to lock to an incoming clock source and produce an output clock available at 110nm...
1292
0.0
Fractional N-PLL
The MXL-PLL-FRAC is a high performance Fractional-N PLL implemented using a digital CMOS technology. It is highly integrated and requires no external ...
1293
0.0
Programmable 5-bit CMOS low-frequency divider
The programmable CMOS low-frequency divider configuration of asynchronous programmable impulse counter, control logic and output buffer. The block i...
1294
0.0
Programmable CMOS PLL high-frequency divider
The divider consists of the input signal preamplifier (buffer), the converter of a differential input signal to an unipolar signal with a supply volta...
1295
0.0
TSMC CL013LP 130nm IoT PLL - 30MHz-275MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
1296
0.0
TSMC CL016G 160nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1297
0.0
TSMC CL016G 160nm Clock Generator PLL - 260MHz-1300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1298
0.0
TSMC CL016G 160nm Clock Generator PLL - 65MHz-325MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1299
0.0
TSMC CL016G 160nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1300
0.0
TSMC CL016G 160nm Deskew PLL - 260MHz-1300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
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