Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow A/D Converter (ADC) (532)
arrow Amplifier (116)
arrow Analog Comparator (18)
arrow Analog Filter (28)
arrow Analog Front Ends (41)
arrow Analog Multiplexer (2)
arrow Analog Subsystems (5)
arrow Clock Synthesizer (98)
arrow D/A Converter (DAC) (225)
arrow DC-DC Converter (96)
arrow DLL (744)
arrow Oscillator (344)
arrow Oversampling Modulator (8)
arrow Power Management (945)
arrow RF Modules (103)
arrow Sensor (53)
arrow Sensors and Monitors (109)
arrow Temperature Sensor (133)
arrow Other (273)
3873 IP
1801
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/200mA, with soft-start, UMC 0.13um HS/FSG process
3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator, UMC 0.13um HS/FSG Logic process....
1802
0.118
DC-DC IP, Step-up PWM Regulator, Input: 3.0V - 3.6V, Output: 5V/100mA, with soft-start, UMC 0.13um HS/FSG process
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process....
1803
0.118
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
1804
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
1805
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
1806
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
1807
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
1808
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
1809
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1810
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
1811
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
1812
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
1813
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
1814
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
1815
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
1816
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
1817
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
1818
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
1819
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1820
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
1821
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
1822
0.118
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process...
1823
0.118
OFDM AFE using UMC 55nm eFlash Process
OFDM AFE using UMC 55nm eFlash Process...
1824
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...
1825
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...
1826
0.118
Linear Regulator IP, HJTC 0.11um eFlash process
3.3V to 1.5V/150mA REG, Linear Regulator, HJTC 0.11um eFlash process....
1827
0.118
Linear Regulator IP, Input: 1.0V - 3.6V, Output: 0.9V/20mA, Standby Current: 0.8uA, UMC 55nm ULP process
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process...
1828
0.118
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process....
1829
0.118
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process
3.3V with 60mA driving capability, Istb=85uA Linear Regulator, UMC 0.18um GII Logic process....
1830
0.118
Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 150mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 process
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process....
1831
0.118
Linear Regulator IP, Input: 2.0V - 3.9V, Output: 1.8V / 70mA, Iq=66uA, Idis=1uA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process....
1832
0.118
Linear Regulator IP, Input: 2.0V-4.0V, Output: 1.8V / 100mA, UMC 0.18um G2 process
3.3V with 100mA driving capability, Istb=100uA Linear Regulator, 0.18um GII Logic process....
1833
0.118
Linear Regulator IP, Input: 2.2 - 3.6V, Output: 1.8V/100mA, HJTC 0.18um eFlash/G2 process
Input 2.2V~3.6V, Output=1.8V, Loading 100mA Regulator, HJTC 0.18um eFlash 1.8V/3.3V/5V process....
1834
0.118
Linear Regulator IP, Input: 2.5V - 5.5V, Output: 1.8V/50mA, Iq=4uA, Idis=0.5uA, HJTC 0.18um eFlash/G2 process
Input 2.5V~5.5V, Output=1.8V, Loading 50mA Regulator, HJTC 0.18um eFlash 1.8V/3.3V/5V process....
1835
0.118
Linear Regulator IP, Input: 2.5V - 5.5V, Output: 3.3V/20mA, HJTC 0.18um eFlash/G2 process
Input 2.5V~5.5V, Output=3.3V, Loading 20mA Regulator, HJTC 0.18um eFlash 1.8V/3.3V/5V process....
1836
0.118
Linear Regulator IP, Input: 3.3V, Output: 1.1V/150mA, UMC 40nm LP process
3.3V to 1.1V with 150mA driving capability, High accuracy Non-trim Linear Regulator, UMC 40nm LP/RVT Low-K Logic process....
1837
0.118
Linear Regulator IP, Input: 3.3V, Output: 1.1V/200mA, UMC 40nm LP process
3.3V to 1.1V/200mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process....
1838
0.118
Linear Regulator IP, Input: 3.3V, Output: 1.2V/1.0V/0.8V, 50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA, Linear Regulator. UMC 0.13um HS/FSG Logic process....
1839
0.118
Linear Regulator IP, Input: 3.3V, Output: 1.8V/150mA, HJTC 0.18um eFlash/G2 process
3.3V to 1.8V with 150mA driving capability, Istb=120uA, Linear Regulator, H.J. 0.18um eFlash process....
1840
0.118
Linear Regulator IP, Input: 3.3V, Output: 1.8V/150mA, UMC 0.18um eFlash/G2 process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.18um eFlash process....
1841
0.118
Linear Regulator IP, Input: 3.3V, Output: 2.5V/100mA, UMC 40nm LP process
3.3V to 2.5V with 100mA driving capability, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process....
1842
0.118
Linear Regulator IP, Input: 4.0-5.5V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um eFlash/G2 process
5V to 3.3V and 1.8V with 250mA and 70mA driving capability, Istb=200uA, Linear Regulator, UMC 0.18um eFlash process....
1843
0.118
Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process....
1844
0.118
Linear Regulator IP, Input: 5.0V, Output: 3.3V/250mA, 1.8V/70mA, HJTC 0.18um eFlash/G2 process
5.0V to 3.3V with 250mA and 1.8V with 70mA driving capability, IQ=180uA, Linear Regulator, HJTC 0.18um eFlash process....
1845
0.118
Linear Regulator IP, Input: 5.0V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um G2 process
5V to 3.3V/1.8V with 250mA/70 mA driving capability, Istb=80uA, Linear Regulator, UMC 0.18um GII Logic process....
1846
0.118
Linear Regulator IP, Output: 1.1V/100mA, UMC 40nm LP process
3.3V to 1.1V with 100mA driving capability, Fast Transient Linear Regulator, UMC 40nm LP/RVT Low-K Logic process....
1847
0.118
Linear Regulator IP, Output: 1.1V/150mA, UMC 40nm LP process
3.3V to 1.1V with 150mA driving capability, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process....
1848
0.118
Linear Regulator IP, Output: 1.2V/100mA, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process 3.3V to 1.2V with 100mA driving capability, High PSRR linear Regulator....
1849
0.118
Linear Regulator IP, Output: 1.2V/100mA, UMC 90nm SP process
2.5V to 1.2V with 100mA driving capability, Istb=50uA, Linear Regulator, UMC 90nm SP/RVT Low-K process....
1850
0.118
Linear Regulator IP, Output: 1.2V/120mA, UMC 0.11um HS/FSG process
3.3V to 1.2V with 120mA driving capability, Linear Regulator, UMC 0.11um HS/FSG Logic process....