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5588 IP
2501
1.0
TSMC CLN28LP 28nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2502
1.0
TSMC CLN28LP 28nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2503
1.0
TSMC CLN28LP 28nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2504
1.0
TSMC CLN28LP 28nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2505
1.0
TSMC CLN28LP 28nm DDR DLL - 189MHz-945MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2506
1.0
TSMC CLN28LP 28nm DDR DLL - 90MHz-450MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2507
1.0
TSMC CLN28LP 28nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2508
1.0
TSMC CLN28LP 28nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2509
1.0
TSMC CLN28LP 28nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2510
1.0
TSMC CLN28LP 28nm General Purpose PLL - 160MHz-800MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2511
1.0
TSMC CLN28LP 28nm Multi Phase DLL - 160MHz-800MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2512
1.0
TSMC CLN28LP 28nm Multi Phase DLL - 320MHz-1600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2513
1.0
TSMC CLN28LP 28nm Multi Phase DLL - 80MHz-400MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2514
1.0
TSMC CLN28LP 28nm Spread Spectrum PLL - 140MHz-700MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2515
1.0
TSMC CLN28LP 28nm Spread Spectrum PLL - 280MHz-1400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2516
1.0
TSMC CLN28LP 28nm Spread Spectrum PLL - 70MHz-350MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2517
1.0
TSMC CLN40G 40nm Clock Generator PLL - 170MHz-850MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2518
1.0
TSMC CLN40G 40nm Clock Generator PLL - 340MHz-1700MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2519
1.0
TSMC CLN40G 40nm Clock Generator PLL - 680MHz-3400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2520
1.0
TSMC CLN40G 40nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2521
1.0
TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2522
1.0
TSMC CLN40G 40nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2523
1.0
TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2524
1.0
TSMC CLN40G 40nm Deskew PLL - 340MHz-1700MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2525
1.0
TSMC CLN40G 40nm Deskew PLL - 680MHz-3400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2526
1.0
TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2527
1.0
TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2528
1.0
TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2529
1.0
TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2530
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2531
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2532
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2533
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2534
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2535
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2536
1.0
TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2537
1.0
TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2538
1.0
TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2539
1.0
TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2540
1.0
TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2541
1.0
TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2542
1.0
TSMC CLN40LP 40nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2543
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 150MHz-750MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2544
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 300MHz-1500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2545
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 75MHz-375MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2546
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2547
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2548
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2549
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2550
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 260MHz-1300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
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