Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5596 IP
2901
0.118
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process...
2902
0.118
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process...
2903
0.118
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm...
2904
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
2905
0.118
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process...
2906
0.118
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process....
2907
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
2908
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
2909
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
2910
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
2911
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process .
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...
2912
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
2913
0.118
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process....
2914
0.118
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process....
2915
0.118
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....
2916
0.118
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process.
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 55nm SP process....
2917
0.118
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process.
Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process....
2918
0.118
Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process...
2919
0.118
Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process...
2920
0.118
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process...
2921
0.118
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process...
2922
0.118
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process...
2923
0.118
Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process
Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process...
2924
0.118
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process...
2925
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process...
2926
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process...
2927
0.118
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process...
2928
0.118
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process...
2929
0.118
Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process
Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process...
2930
0.118
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process
Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process...
2931
0.118
internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process
internal-R, frequency 32.768MHz RC OSC. Input 0.9V±10% or 1.2V±10% ; UMC 55 nm EFLASH process...
2932
0.118
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process...
2933
0.118
Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process.
Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process....
2934
0.118
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
2935
0.118
Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process
Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process...
2936
0.118
Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process
Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process...
2937
0.118
Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
2938
0.118
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x005F_x005F_x005F_x000D_
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process....
2939
0.118
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process.
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm LP process....
2940
0.118
NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process.
NO External-R ,frequency 32.768KHz , Oscillator . Input 0.9V+/-10%; UMC 55nm ULP process....
2941
0.118
NO External-R ,frequency 32.768MHz , Oscillator . Input 0.9V+/-10% ,1.2V+/-10% ; UMC 55nm ULP process.
NO External-R ,frequency 32.768MHz , Oscillator . Input 0.9V+/-10% ,1.2V+/-10% ; UMC 55nm ULP process....
2942
0.118
Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power supply monitoring system; UMC 55nm eFlash Process
Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power ...
2943
0.118
Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process
Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process...
2944
0.118
Voltage Detector IP, 3 Levels, UMC 0.18um G2 process
3-level detector for MMC flash storage, VCCA=3.3V, Ivcca=65uA, UMC 0.18um GII Logic process....
2945
0.118
Voltage Detector IP, 4 Levels, HJTC 0.18um eFlash/G2 process
4-level detector for USB applications, input 3.3V, Ivcca=115uA, HJTC 0.18um embedded flash (P-channel cell) process....
2946
0.118
Voltage Detector IP, 4 Levels, UMC 0.11um HS/AE process
4-level detector for USB-OTG applications, input 3.3V, UMC 0.11um HS/AE Logic process....
2947
0.118
Voltage Detector IP, 4 Levels, UMC 0.13um HS/FSG process
4-level voltage detector for USB_OTG, UMC 0.13um HS/FSG Logic process....
2948
0.118
Voltage Detector IP, 4 Levels, UMC 0.13um LL/FSG process
4-level voltage detector, input 1.2V, Ivcca=65uA, UMC 0.13um LL-LVT(FSG) process....
2949
0.118
Voltage Detector IP, 4 Levels, UMC 0.153um G2 process
4-level detector for USB-OTG, VCCA=3.3V, Ivcca=125uA, UMC 0.153um 1.8V/3.3V GII Logic process....
2950
0.118
Voltage Detector IP, 4 Levels, UMC 0.18um G2 process
4-level voltage detector for MP3, UMC 0.18um GII Logic process....