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5494 IP
3151
0.118
UMC 55uLP_x005F_x005F_x005F_x000D_ ADC
UMC 55uLP ADC...
3152
0.118
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process...
3153
0.118
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....
3154
0.118
Analog Comparator; 0.25um Logic process
Analog Comparator; 0.25um Logic process...
3155
0.118
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications. FXAFE010HF0A is fabricated in UMC 55nm SP, low-k, logic process to enab...
3156
0.118
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process...
3157
0.118
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process...
3158
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process...
3159
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process...
3160
0.118
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process...
3161
0.118
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process...
3162
0.118
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process
Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process...
3163
0.118
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process
Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process...
3164
0.118
Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process
Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40n...
3165
0.118
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process...
3166
0.118
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process...
3167
0.118
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Input 1M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process...
3168
0.118
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process...
3169
0.118
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process...
3170
0.118
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x005F_x005F_x000D_
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process...
3171
0.118
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process...
3172
0.118
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process...
3173
0.118
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process
Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process...
3174
0.118
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process...
3175
0.118
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process...
3176
0.118
Input 20M-66M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process
Input 20M-66M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process...
3177
0.118
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process...
3178
0.118
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process...
3179
0.118
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process.
Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process....
3180
0.118
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process
Input 2M-200M Hz, output 12M-300MHz, frequency synthesizable PLL; UMC 0.13um CMOS image sensor process...
3181
0.118
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process....
3182
0.118
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....
3183
0.118
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3184
0.118
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process...
3185
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
3186
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
3187
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...
3188
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
3189
0.118
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Pr...
3190
0.118
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process
Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Pro...
3191
0.118
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3192
0.118
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process...
3193
0.118
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic...
3194
0.118
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process
Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm ...
3195
0.118
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process...
3196
0.118
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process
Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process...
3197
0.118
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm...
3198
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
3199
0.118
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process
Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process...
3200
0.118
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process....