Design & Reuse
5588 IP
3301
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 60MHz - 200MHz, UMC 0.18um G2 process
Input 5M-200MHz, output 60M-200MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....
3302
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.162um LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.162um Logic process....
3303
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um eFlash/G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.18um eFlash process....
3304
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.18um GII Logic process....
3305
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, 0.18um GII Logic process....
3306
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.18um LL process
UMC 0.18um LL process Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL....
3307
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 65nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 65nm LL/RVT process....
3308
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process....
3309
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process....
3310
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 50MHz - 300MHz, UMC 90nm LL process
Input 5MHz-300MHz, output 50MHz-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process....
3311
0.118
PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process....
3312
0.118
PLL (Frequency Synthesizer) IP, Input: 66.66MHz, Output: 400MHz - 800MHz, UMC 0.13um HS/FSG process
Input 66.66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process....
3313
0.118
PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process....
3314
0.118
PLL (Frequency Synthesizer) IP, Input: 80MHz - 150MHz, Output: 80MHz - 150MHz, UMC 0.13um HS/FSG process
Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process....
3315
0.118
PLL (Mini-PLL) IP, Input: 20MHz - 200MHz, Output: 31.5MHz - 500MHz, UMC 65nm SP process
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 31.5MHz and 500MHz, UMC 65nm SP/RVT Low-K Logic process....
3316
0.118
PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process
UMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator....
3317
0.118
PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process
5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process....
3318
0.118
PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process
Input 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process....
3319
0.118
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process....
3320
0.118
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process....
3321
0.118
DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 0.11um HS/FSG process
Input 100M~400MHz, Output 100M~400MHz DLL-based cell that generates two-channel DQS with 25% timing delay, UMC 0.11um HS/RVT Logic process....
3322
0.118
PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process
This Phase-Locked Loop (PLL) based clock multiplier....
3323
0.118
PLL IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process
Output frequency 25M~400MHz PLL, UMC 0.13um SP/FSG Logic process....
3324
0.118
DLL IP, Input: 18MHz - 45MHz, Output: 18 - 45MHz, UMC 90nm SP process
Input 18M-45MHz, output 18M-45MHz, timing generator DLL, UMC 90nm SP/RVT Low-K process....
3325
0.118
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process....
3326
0.118
PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process
Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process....
3327
0.118
PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for JitteRClean Mode. UMC 4...
3328
0.118
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process....
3329
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process
Input 32.768KHz, output 12M-30MHz, PLL, UMC 90nm SP/RVT Logic Low-K process....
3330
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process
Input 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process....
3331
0.118
PLL IP, Input: 32.768KHz, Output: 12MHz, UMC 0.153um G2 process
Input 32.768KHz, output 12MHz, PLL, UMC 0.153um GII Logic/MM process....
3332
0.118
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process
Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL, UMC 0.13um HS/FSG Logic process....
3333
0.118
PLL IP, Input: 372M - 540MHz, Output: 5MHz - 420MHz, UMC 0.11um HS/FSG process
Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL, UMC 0.11um HS/FSG Logic process....
3334
0.118
DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF, UMC 28nm Logic and Mi...
3335
0.118
DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
3336
0.118
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process
DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...
3337
0.118
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system...
3338
0.118
UMC 40nm high performance mono audio codec with highly integrated analog functionality system
UMC 40nm high performance mono audio codec with highly integrated analog functionality system...
3339
0.118
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%....
3340
0.118
UMC 55uLP_x005F_x005F_x005F_x000D_ ADC
UMC 55uLP ADC...
3341
0.118
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process...
3342
0.118
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....
3343
0.118
Analog Comparator; 0.25um Logic process
Analog Comparator; 0.25um Logic process...
3344
0.118
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications. FXAFE010HF0A is fabricated in UMC 55nm SP, low-k, logic process to enab...
3345
0.118
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process...
3346
0.118
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process...
3347
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process...
3348
0.118
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process...
3349
0.118
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process...
3350
0.118
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process...