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5619 IP
4401
0.0
Ultra low Power High Speed 800MHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 800MHz is required to lock to an incoming clock source and produce an output clock available at 110nm....
4402
0.0
Ultra Low Power PMU - Shunt regulator SilTerra 0.18 μm
This macro-cell is an ultra low consumption Power Management Unit (PMU) core designed for Silterra 0.18µm C18G CMOS technology TO (thick oxide) and HP...
4403
0.0
Ultra Low Power PMU - Ultra Low Voltage (Vin > 1.2V), Ultra Low Power (6µW) LFoundry 0.15 μm
This macro-cell is an ultra low consumption Power Management Unit (PMU) core designed for LFoundry 0.15µm LF150 CMOS technology STD (Standard) and LP ...
4404
0.0
Ultra low-power crystal-based 32 kHz oscillator designed in TSMC 12FFC+
The OSC-XT-32k-T12FFC.01 IP is an ultra-low power crystal-based oscillator designed in TSMC 12 nm FF for accurate 32 kHz clock generation in the SoC A...
4405
0.0
Ultra low-power crystal-based 32 kHz oscillator designed in TSMC 22ULL
This 32 kHz crystal oscillator is an excellent choice for IoT SoC designed in TSMC 22nm ULL technology with stringent power consumption constraints. I...
4406
0.0
Ultra-low power 32 kHz RC oscillator designed in TSMC 22ULL
Ultra-low power 32 kHz RC oscillator designed in TSMC 22ULL for IoT SoC and ULP MCU applications requiring fast wake-up....
4407
0.0
Ultra-low power 32 kHz RC oscillator in TSMC 40 ULP eFlash
Ultra-low power 32 kHz RC oscillator designed in TSMC 40 ULP eFlash for IoT SoC and ULP MCU applications requiring fast wake-up....
4408
0.0
Ultra-low power 32 kHz XTAL oscillator designed in Samsung Foundries 65nm
Ultra-low power 32 kHz XTAL oscillator designed in Samsung Foundries 65nm LFR6LP (eFlash process) for IoT applications and ULP MCU applications...
4409
0.0
Ultra-low Power Voltage Reference
...
4410
0.0
Ultra-low quiescent capacitor-less LDO voltage regulator in Samsung Foundries 65nm LFR6LP
The qLR-Della-cl-ref-[1.8-5.5]-[0.9-1.4].02 is an ultra-low-quiescent and capacitor-less linear regulator used to supply SoC always-on domain. It is d...
4411
0.0
3mA LDO voltage regulator (1.3V – 3.6V to 1.2V/1.3V/1.5V/1.65V)
130GF_LDO_01 is a capacitor-less regulator designed to supply integrated circuits with stable and precise voltage. The LDO inputs voltage VDD 1.3… 3...
4412
0.0
5mA LDO voltage regulator (output voltage value 1.15V/1.2 V/1.25V/1.3V) with BG (0.6V) and I2V (5uA, 10uA, 20uA, 50uA)
130GF_LDO_03 is a Power management unit, designed to supply integrated circuits with stable and precise voltage. IP includes Bandgap block (BG), Volta...
4413
0.0
UMC 130nm Bandgap
The OT0118 is a medium precision, bandgap voltage reference and current reference generator specifically tuned for the UMC 130nm CMOS process....
4414
0.0
UMC L110AELL 110nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4415
0.0
UMC L110AELL 110nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4416
0.0
UMC L110AELL 110nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4417
0.0
UMC L110AELL 110nm DDR DLL - 24MHz-120MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4418
0.0
UMC L110AELL 110nm DDR DLL - 32MHz-160MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4419
0.0
UMC L110AELL 110nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4420
0.0
UMC L110AELL 110nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4421
0.0
UMC L110AELL 110nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4422
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4423
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 30MHz-150MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4424
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4425
0.0
UMC L110HS 110nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4426
0.0
UMC L110HS 110nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4427
0.0
UMC L110HS 110nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4428
0.0
UMC L110HS 110nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4429
0.0
UMC L110HS 110nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4430
0.0
UMC L110HS 110nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4431
0.0
UMC L110HS 110nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4432
0.0
UMC L110HS 110nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4433
0.0
UMC L110HS 110nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4434
0.0
UMC L110HS 110nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4435
0.0
UMC L110HS 110nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4436
0.0
UMC L110LL 110nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4437
0.0
UMC L110LL 110nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4438
0.0
UMC L110LL 110nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4439
0.0
UMC L110LL 110nm DDR DLL - 24MHz-120MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4440
0.0
UMC L110LL 110nm DDR DLL - 32MHz-160MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
4441
0.0
UMC L110LL 110nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4442
0.0
UMC L110LL 110nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4443
0.0
UMC L110LL 110nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
4444
0.0
UMC L110LL 110nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4445
0.0
UMC L110LL 110nm Spread Spectrum PLL - 30MHz-150MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4446
0.0
UMC L110LL 110nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
4447
0.0
UMC L110SP 110nm Clock Generator PLL - 118MHz-590MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4448
0.0
UMC L110SP 110nm Clock Generator PLL - 236MHz-1180MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4449
0.0
UMC L110SP 110nm Clock Generator PLL - 59MHz-295MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
4450
0.0
UMC L110SP 110nm DDR DLL - 57MHz-285MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...