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633 IP
301
0.118
DFI Wrapper
DFI Wrapper...
302
0.118
UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device
UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device...
303
0.118
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage...
304
0.118
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage...
305
0.118
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces
Combo DDR34/LPDDR23 Controller with 8 ports AHB/AXI interfaces...
306
0.118
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
307
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
308
0.118
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
309
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
310
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
311
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
312
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
313
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
314
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS....
315
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
316
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT...
317
0.118
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....
318
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
319
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
320
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process...
321
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version...
322
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process...
323
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process...
324
0.118
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process...
325
0.0
HBM3 PHY IP for TSMC N4
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
326
0.0
HBM3 PHY IP on TSMC N5
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
327
0.0
HBM3 PHY on TSMC N3P
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
328
0.0
GDDR2 Controller IP
GDDR2 interface provides full support for the GDDR2 interface, compatible with GDDR2 specification and DFI-version 4.0 or 5.0 Specification Compliant....
329
0.0
GDDR3 Controller IP
GDDR3 interface provides full support for the GDDR3 interface, compatible with GDDR3 specification and DFI-version 4.0 or 5.0 Specification Compliant....
330
0.0
GDDR3L Controller IP
GDDR3L interface provides full support for the GDDR3L interface, compatible with GDDR3L specification and DFI-version 4.0 or 5.0 Specification Complia...
331
0.0
GDDR4 Controller IP
GDDR4 interface provides full support for the GDDR4 interface, compatible with GDDR4Spec_rev_04 specification and DFI-version 4.0 or 5.0 Specification...
332
0.0
GDDR5 Controller IP
GDDR5 interface provides full support for the GDDR5 interface, compatible with standard JESD212C specification and DFI-version 4.0 or 5.0 Specificatio...
333
0.0
GDDR5X Controller IP
GDDR5X interface provides full support for the GDDR5X interface, compatible with standard JESD232 and JESD232A specification and DFI-version 4.0 or 5....
334
0.0
GDDR6 Controller IP
GDDR6 interface provides full support for the GDDR6 interface, compatible with standard JESD250, JESD250A and JESD250B specification with version 3.06...
335
0.0
GDDR6 Memory PHY for TSMC N5P
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
336
0.0
GDDR6 Memory PHY for TSMC N7
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
337
0.0
GDDR6 PHY for TSMC N6
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
338
0.0
GDDR6X Controller IP
GDDR6X interface provides full support for the GDDR6X interface, compatible with GDDR6X protocol draft specification and DFI-version 4.0 or 5.0 Specif...
339
0.0
GDDR7 Memory PHY for TSMC N3P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
340
0.0
GDDR7 Memory PHY for TSMC N4P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
341
0.0
GDDR7 Memory PHY for TSMC N5P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
342
0.0
DDR 4/3 Memory Controller IP - 2400MHz
This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and ...
343
0.0
DDR Controller IP
DDR interface provides full support for the DDR interface, compatible with JESD79F specification. Through its DDR compatibility, it provides a simple ...
344
0.0
DDR Memory Controller IP for low power and high reliability
DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Specification Compliant...
345
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DDR123/LPDDR23 in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
346
0.0
DDR2 Controller IP
DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification. Through its DDR2 compatibility, it provides a si...
347
0.0
DDR2 SDRAM Controller IP
DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification and DFI-version 2.0 or higher Specification Compl...
348
0.0
DDR2,3/LPDDR2,3 combo DDR PHY+ Controller upto 1333Mbps in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
349
0.0
DDR23/LPDDR23 in SMIC 40NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
350
0.0
DDR23/LPDDR23 PHY+Controller in SMIC 28HKD 0.9/2.5V
DDR23/LPDDR23 combo DDR PHY + Controller upto 1600Mbps for IoT application...