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Browse Memory Controller & PHY
DDR (672)
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672 IP
301
0.118
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....
302
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
303
0.118
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
304
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process...
305
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version...
306
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process...
307
0.118
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process...
308
0.118
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process...
309
0.0
HBM3 PHY IP for TSMC N4
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
310
0.0
HBM3 PHY IP on TSMC N5
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
311
0.0
HBM3 PHY on TSMC N3P
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
312
0.0
UCIe Chiplet PHY & Controller in Global Foundries (12 nm, 14 nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
313
0.0
UCIe Chiplet PHY & Controller in Samsung (8nm, 10nm, 14nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
314
0.0
UCIe Chiplet PHY & Controller in SMIC (14 nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
315
0.0
UCIe Chiplet PHY & Controller in TSMC (3nm, 4nm, 5nm, 7nm, 10nm, 12nm, 16nm)
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
316
0.0
GDDR2 Controller IP
GDDR2 interface provides full support for the GDDR2 interface, compatible with GDDR2 specification and DFI-version 4.0 or 5.0 Specification Compliant....
317
0.0
GDDR3 Controller IP
GDDR3 interface provides full support for the GDDR3 interface, compatible with GDDR3 specification and DFI-version 4.0 or 5.0 Specification Compliant....
318
0.0
GDDR3L Controller IP
GDDR3L interface provides full support for the GDDR3L interface, compatible with GDDR3L specification and DFI-version 4.0 or 5.0 Specification Complia...
319
0.0
GDDR4 Controller IP
GDDR4 interface provides full support for the GDDR4 interface, compatible with GDDR4Spec_rev_04 specification and DFI-version 4.0 or 5.0 Specification...
320
0.0
GDDR5 Controller IP
GDDR5 interface provides full support for the GDDR5 interface, compatible with standard JESD212C specification and DFI-version 4.0 or 5.0 Specificatio...
321
0.0
GDDR5X Controller IP
GDDR5X interface provides full support for the GDDR5X interface, compatible with standard JESD232 and JESD232A specification and DFI-version 4.0 or 5....
322
0.0
GDDR6 Controller IP
GDDR6 interface provides full support for the GDDR6 interface, compatible with standard JESD250, JESD250A and JESD250B specification with version 3.06...
323
0.0
GDDR6 Memory PHY for TSMC N5P
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
324
0.0
GDDR6 Memory PHY for TSMC N7
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
325
0.0
GDDR6 PHY for TSMC N6
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
326
0.0
GDDR6X Controller IP
GDDR6X interface provides full support for the GDDR6X interface, compatible with GDDR6X protocol draft specification and DFI-version 4.0 or 5.0 Specif...
327
0.0
GDDR7 Memory PHY for TSMC N3P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
328
0.0
GDDR7 Memory PHY for TSMC N4P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
329
0.0
GDDR7 Memory PHY for TSMC N5P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
330
0.0
DDR 4/3 Memory Controller IP - 2400MHz
This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and ...
331
0.0
DDR Memory Controller IP for low power and high reliability
DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Specification Compliant...
332
0.0
DDR123/LPDDR23 in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
333
0.0
DDR2 SDRAM Controller IP
DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification and DFI-version 2.0 or higher Specification Compl...
334
0.0
DDR2,3/LPDDR2,3 combo DDR PHY+ Controller upto 1333Mbps in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
335
0.0
DDR23/LPDDR23 in SMIC 40NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
336
0.0
DDR23/LPDDR23 PHY+Controller in SMIC 28HKD 0.9/2.5V
DDR23/LPDDR23 combo DDR PHY + Controller upto 1600Mbps for IoT application...
337
0.0
DDR3 Controller IP
The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing th...
338
0.0
DDR3 Memory Controller
Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full progra...
339
0.0
DDR3 PHY
Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-m...
340
0.0
DDR3 SDRAM Controller IP with advance feautures package
DDR3 interface provides full support for the DDR3 interface, compatible with JESD79-3F specification and DFI-version 2.0 or higher Specification Compl...
341
0.0
DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps and DDR2 DRAM speeds ...
342
0.0
DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throughput. The DDR IP is c...
343
0.0
DDR3/3L Controller IP
SmartDV’s DDR3/3L Controller IP is a silicon-proven, high-performance solution designed to enable efficient memory interfacing for a wide range of app...
344
0.0
DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible S...
345
0.0
DDR3/3L/2/LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR3/3L/2/LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
346
0.0
DDR3/3L/DDR4/LPDDR4 PHY
The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-...
347
0.0
DDR34/LPDDR23 in SMIC 40NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
348
0.0
DDR34/LPDDR34 PHY in SMIC 28HKC+
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
349
0.0
DDR34/LPDDR34 PHY in SMIC 28HKD 0.9/1.8V
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
350
0.0
DDR34/LPDDR34 PHY in SMIC 28HKD 0.9/2.5V
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
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