Memory Controller - PHY IP IP Core

Browse Memory Controller & PHY

DDR (633)

eMMC (20)

Flash Controller (8)

HBM (31)

Mobile SDR Controller (4)

SDRAM Controller (107)

SRAM Controller (3)

Other (21)

You must be registered with the D&R website to view the full search results, including:

Complete datasheets for IP Core products
Contact information for IP Core suppliers

Please log in here to your account.

New user ? Signup here.

351

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

352

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

353

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

354

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

355

0.118

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...

356

0.118

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...

357

0.118

SD Host Controller IP, SD host spec. v3.0, SDIO spec. v2.0, MMC spec. v4.3, Supports UHS50/UHS104 card, Soft IP

SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00....

358

0.118

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

359

0.118

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

360

0.118

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...

361

0.118

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...

362

0.118

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...

363

0.118

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...

364

0.118

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...

365

0.118

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...

366

0.118

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...

367

0.118

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process...

368

0.118

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process...

369

0.118

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...

370

0.118

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...

371

0.118

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process...

372

0.118

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process...

373

0.118

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess...

374

0.118

DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP

DDR2/3 Combo SDRAM Controller....

375

0.118

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process...

376

0.118

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process...

377

0.118

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process...

378

0.118

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process...

379

0.118

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process...

380

0.118

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device...

381

0.118

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device...

382

0.118

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

383

0.118

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process...

384

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process...

385

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process...

386

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process...

387

0.118

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process...

388

0.118

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device...

389

0.118

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage...

390

0.118

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device...

391

0.118

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device...

392

0.118

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)...

393

0.118

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...

394

0.118

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...

395

0.118

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process...

396

0.118

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process...

397

0.118

DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...

398

0.118

DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS

DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS...

399

0.118

DDR3 RTL PHY Address Command module

DDR3 RTL PHY Address Command module...

400

0.118

DDR3 RTL PHY data module

DDR3 RTL PHY data module...

10|

...|