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12 IP
1
33.0
General Purpose & Bridge DMA
LeWiz provides a range of direct memory access controllers (DMA) and bus bridge IP cores. These are customizable to user’s SoC or design requirements....
2
13.0
AMBA Parameter Configurable Multi-Channel DMA Controller (typically 1 to 256)
The Digital Blocks DB-DMAC-MC-AMBA SystemVerilog RTL IP Core is a Scatter-Gather (SG) Direct Memory Access (DMA) Controller with Master AXI4 Interconn...
3
12.0
AHB Multi-Channel DMA Controller
The Digital Blocks DB-DMAC-MC-AHB Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memor...
4
5.0
AXI4 Multi-Channel DMA Controller (fixed 2,4,8,16 DMA Channels)
The Digital Blocks DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 2, 4, 8, or 16 independent data transfers. The Dire...
5
0.0
AHB Scatter-Gather DMA Controller
The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral data ...
6
0.0
Direct Memory Access Controller IP Core
The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...
7
0.0
DMA Controller with AHB IP
DMA Controller with AHB interface is full featured, easy-to-use, synthesizable design that can be used with AHB based systems as a controller to trans...
8
0.0
DMA Controller with AXI IP
DMA Controller with AXI interface is full featured, easy-to-use, synthesizable design that can be used with AXI based systems as a controller to trans...
9
0.0
DMA Controller with OCP IP
DMA Controller with OCP interface is full featured, easy-to-use, synthesizable design that can be used with OCP based systems as a controller to trans...
10
0.0
DMA Controller with TileLink IP
DMA Controller with TileLink interface is full featured, easy-to-use, synthesizable design that can be used with TileLink based systems as a controlle...
11
0.0
AXI4 to/from AXI4-Stream Scatter-Gather DMA
The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the ho...
12
0.0
AXI4 to/from Stream DMA
The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AX...
