Design & Reuse
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19 IP
1
25.0
1G/10G TCP/IP Hardware Stack
The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to...
2
12.0
SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process Fully in compliance with ANSI, Bellcore...
3
12.0
USB 2.0 OTG On-The-Go Transceiver PHY
SMS USB 2.0 OTG Transceiver is LS/FS/HS compliant with USB 2.0 specification and includes VBUS comparators, Switched Pullup & Pulldown resistors, data...
4
10.0
100G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
5
10.0
40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
6
10.0
NTP Server core
NetTimeLogic’s NTP Server is a full hardware (FPGA) only implementation of a SNTPv4 Server according to RFC 4330/5905. It supports hardware timestampi...
7
6.0
OSU processor, optimized for E1/FE/GE services with Ethernet over SDH over OTU0/OTU1 lines
The TPS3215MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3215MP processors accept 4x FE/GE and 4x E1 client signals, process a...
8
6.0
OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines
The TPS3204MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3204MP processors accept 4x STM1/STM4/FE/GE and 4x E1 client signals,...
9
5.0
DiFi IP core
The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 ...
10
4.0
Smart Grid PLC Baseband Processor
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including ...
11
4.0
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...
12
1.0
10G/25G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
13
1.0
UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...
14
0.0
ETHERNET 100G PCS IP
SmartDV’s Ethernet 100G PCS (Physical Coding Sublayer) IP Core is designed to meet the rigorous demands of high-speed data transmission across network...
15
0.0
ETHERNET 1G PCS IP
SmartDV’s Ethernet 10M/100M/1G PCS (Physical Coding Sublayer) IP Core is a silicon-proven, compact solution for implementing the data coding and trans...
16
0.0
ETHERNET 25G PCS IP
SmartDV’s Ethernet 25G PCS (Physical Coding Sublayer) IP Core provides a reliable, high-speed data path between the MAC and the PMA/PHY layers for 25 ...
17
0.0
Ethernet 40G PCS IP
SmartDV’s Ethernet 40G PCS (Physical Coding Sublayer) IP Core delivers the essential link-layer processing required for 40 Gigabit Ethernet systems. B...
18
0.0
Ethernet 50G PCS IP
SmartDV’s Ethernet 50G PCS (Physical Coding Sublayer) IP Core is engineered to support reliable and high-speed data communication across a wide range ...
19
0.0
ETHERNET Switch IP
Ethernet Switch core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet IEEE standards. Through its Ethernet compati...