Design & Reuse
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (147)
arrow Ethernet (171)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (37)
arrow Other (14)
415 IP
151
5.0
NTP Client core
NetTimeLogic’s NTP Clientis a full hardware (FPGA) only implementation of a SNTPv4 Client according to RFC 4330/5905. It supports hardware timestampin...
152
5.0
DVB-S2X Wideband LDPC BCH Decoder IP Core
The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 ...
153
5.0
DVB-T2 Demodulator and LDPC/ BCH Decoder IP Core
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to cont...
154
5.0
Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core
NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...
155
4.0
40G UDP IP Stack
Logic Fruit’s 40G UDP IP Stack implements a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connection or LAN....
156
4.0
10G UDP IP Stack
This 10G UDP IP Stack carries out the implementation of a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connec...
157
4.0
56G Ethernet PHY (8nm)
The Ethernet PHY IP consists of hardmacro PMA, PMD and softmacro PCS compliant to IEEE 802.3 Ethernet specification. This IP offers a cost-effective a...
158
4.0
Reed Solomon Decoder IP Core
A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...
159
4.0
Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...
160
4.0
1G UDP IP Stack
Logic Fruit’s 1G UDP IPⓇ is specialized in data transmission and reception over the internet. The UDP Protocol helps to establish a low-latency and lo...
161
4.0
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several ...
162
4.0
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive un...
163
4.0
Smart Grid PLC Baseband Processor
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including ...
164
4.0
Interleaver / De-interleaver
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding....
165
4.0
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...
166
4.0
Configurable Reed Solomon Decoder
Highly configurable Reed Solomon Decoder compliant with the requirements of nearly all modern standards using Reed-Solomon error correction....
167
4.0
Configurable Reed Solomon Encoder
A fully configurable Reed Solomon Encoder compliant with the requirements of nearly all modern standards that use Reed-Solomon error correction....
168
4.0
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system. The receiver extracts the phase and magnitude of the ca...
169
4.0
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
170
4.0
Configurable Viterbi Decoder
Highly configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction....
171
4.0
Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading. Therefore it is necessary to identify and invert the discrete transfer function of t...
172
4.0
ETHERNET 10G MAC
The 10G Ethernet MAC core is a thoroughly verified Ethernet Media Access Controller function that interfaces with physical layer devices in an Etherne...
173
4.0
ITU G.704 E1 Framer/Deframer
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
174
4.0
ITU G.704 T1 Framer/Deframer
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
175
4.0
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
176
3.0
2.3 Gbit/s DOCSIS 3.1 Downstream LDPC Decoder (PLC, NCP, Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth d...
177
3.0
100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates ...
178
3.0
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane...
179
3.0
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...
180
3.0
19 GHz to 20.25 GHz FMCW Modulator for RADAR
The WEA20SFMCWI22G is an ultra-linear FMCW modulator consisting of 3 integrated PLLs. One PLL provides a high frequency Reference signal and the other...
181
3.0
MAC - DMAC-RMII - 10/100 Mb Media Access Controller with RMII
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with ...
182
3.0
IEEE 802.11ad (WiGig) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It ...
183
3.0
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on hi...
184
3.0
1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity. John Porter, CTO of Ca...
185
3.0
Wideband DDC
The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples wi...
186
3.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
187
3.0
Fixed-Point AWGN Channel
The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP was developed with the aim o...
188
3.0
GMR Release 2 and GMR Release 3 LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GM...
189
3.0
Open Source Viterbi Decoder (AXI4-Stream compliant)
Convolutional codes are widely adopted in wireless communication systems for forward error correction. Creonic offers you an open source Viterbi decod...
190
3.0
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks....
191
3.0
DVB-RCS2 Modulator
The Creonic DVB-RCS2 modulator is a low-complexity high-performance solution that allows for symbol rates of up to 160 MSymb/s on state-of-the-art FPG...
192
3.0
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....
193
3.0
DVB-S2 Demodulator
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....
194
2.5
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
195
2.5
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
196
2.5
Ethernet MAC 10G SFP
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification. It is designed to be con...
197
2.0
MAC Privacy Protection IP
The MAC Privacy Protection IP is a fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy as standardized in IEEE ...
198
2.0
BCH Encoder/Decoder
The binary BCH decoder has four main functional blocks along with memory blocks: 1. Syndrome calculation block: identifies the presence of errors in ...
199
2.0
CCSDS AR4JA LDPC Encoder & Decoder
The Creonic CCSDS AR4JA LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block l...
200
2.0
CCSDS LDPC
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