Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (152)
arrow Ethernet (177)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (35)
arrow Other (15)
425 IP
201
2.0
CCSDS LDPC
...
202
2.0
LDPC Decoder for DVB-C2
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
203
2.0
Reed Solomon Encoder/Decoder
- The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order ...
204
2.0
IEEE 802.11ad (WiGig) LDPC Decoder
The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It ...
205
2.0
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on hi...
206
2.0
Gigabit Ethernet 802.3 MAC - Media Access Controller
The Gigabit Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The Gigabit Ethernet - ...
207
2.0
Binary-FSK Demodulator
16-bit BFSK demodulator with complex or real data samples. Suitable for passband or baseband operation. Ideal for use in low cost / low power RF ap...
208
2.0
Binary-PSK Demodulator
16-bit BPSK demodulator ideal for low-cost radio links over a few 100m. Features automatic carrier lock with no complex PLL setup or tuning required. ...
209
2.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors...
210
2.0
Fixed-Point AWGN Channel
The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP was developed with the aim o...
211
2.0
GMR Release 2 and GMR Release 3 LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GM...
212
2.0
LTE Turbo decoder
This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code ...
213
2.0
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks....
214
2.0
DVB-RCS Turbo Decoder
DVB-RCS (Digital Video Broadcasting - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmi...
215
1.0
10 Gigabit Ethernet XGMAC IP
Arasan’s 10 Gigabit Ethernet Media Access Controller (XGMAC) IP is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface betw...
216
1.0
Packet-based Digital Radio Link
Fully custom Digital Radio Link based on either our FSK or PSK modulation schemes. Data is split into packets or frames and modulated for transmissio...
217
1.0
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexi...
218
1.0
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
219
1.0
Gigabit Ethernet MAC with AVB
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard. In addition, the Gigabit Ethernet MAC...
220
1.0
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based ...
221
1.0
High Throughput QAM Demapper
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator. The core is capable of accepting a new equa...
222
1.0
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes an...
223
1.0
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equiva...
224
1.0
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 AC...
225
1.0
HomePlug Turbo Decoder
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...
226
1.0
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
227
0.3729
A bridge to convert the slave SPI interface to the master I2C interface and vice versa
The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....
228
0.3729
A bridge to convert the slave SPI interface to the master UART interface and vice versa
The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....
229
0.118
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature....
230
0.118
10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....
231
0.118
10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process
10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process....
232
0.118
10/100 Ethernet PHY IP, UMC 0.18um MS process
10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process....
233
0.118
10/100 Ethernet PHY IP, UMC 65nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process....
234
0.118
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process....
235
0.118
10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_
10/100/1000 ETHERNET CONTROLLER WITH AHB AND AXI BUS...
236
0.118
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
237
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process...
238
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
239
0.118
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process...
240
0.118
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....
241
0.118
Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP
10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....
242
0.118
Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
10/100/1000 Ethernet Controller with AHB bus....
243
0.0
4-channel ATSC 8VSB Modulator
The IPrium-ATSC-8VSB-Modulator IP Core implements the USA DTV standard ATSC A/53 Part 2. The IP Core contains Scrambler, RS Encoder, Trellis Encoder, ...
244
0.0
D-MAC-10/100
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...
245
0.0
2.5G BaseT Ethernet PHY IP in TSMC 22ULL
The 2.5G BaseT Ethernet PHY IP Core provides a robust, production-proven physical layer solution for SoCs requiring high-speed, low-power Ethernet con...
246
0.0
2.5G BaseT Ethernet PHY IP in TSMC 28HPC+
The 2.5G BaseT Ethernet PHY IP built on the 28nm process delivers a cost-effective and performance-optimized physical layer solution for a broad spect...
247
0.0
1.6T Ethernet MAC Controller IP
The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simp...
248
0.0
G.9960 LDPC Decoder
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in th...
249
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency. It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G ope...
250
0.0
10/100/1000 MBit Ethernet MAC
The GigaBit Ethernet Media Access Controller (GRETH_GBIT) supports 10/100/1000 MBit speed in both full- and half-duplex operation. The dataflow is han...