Design & Reuse
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arrow Optical/Telecom (37)
arrow Other (14)
417 IP
201
2.0
UltraFast BCH Decoder
BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic Ultra-fast BCH Decoder is capable of processing an ...
202
2.0
LTE Turbo decoder
This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code ...
203
2.0
ITU 25G PON LDPC Encoder and Decoder
The ITU-T G.9804.2 Recommendation defines the common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks. As part of the ...
204
2.0
DVB-GSE Encapsulator and Decapsulator
The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of s...
205
2.0
DVB-RCS Turbo Decoder
DVB-RCS (Digital Video Broadcasting - Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmi...
206
2.0
DVB-RCS2 Turbo Decoder
DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
207
1.0
10 Gigabit Ethernet XGMAC IP
Arasan’s 10 Gigabit Ethernet Media Access Controller (XGMAC) IP is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface betw...
208
1.0
Packet-based Digital Radio Link
Fully custom Digital Radio Link based on either our FSK or PSK modulation schemes. Data is split into packets or frames and modulated for transmissio...
209
1.0
CCSDS 131.2 Wideband Demodulator
The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver. It allows for processing symbol rates of 500 Msymb/s ...
210
1.0
CCSDS 131.2 Wideband Modulator
The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional...
211
1.0
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 5...
212
1.0
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient u...
213
1.0
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexi...
214
1.0
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
215
1.0
5G-NR LDPC Decoder
5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfil...
216
1.0
Gigabit Ethernet MAC with AVB
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard. In addition, the Gigabit Ethernet MAC...
217
1.0
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based ...
218
1.0
High Throughput QAM Demapper
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator. The core is capable of accepting a new equa...
219
1.0
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes an...
220
1.0
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equiva...
221
1.0
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 AC...
222
1.0
HomePlug Turbo Decoder
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...
223
1.0
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
224
1.0
SPI Master Serial Interface Controller
Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be controll...
225
1.0
SPI Slave Serial Interface Controller
Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The con...
226
1.0
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...
227
1.0
DVB-S2X Demodulator
The Creonic DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FP...
228
1.0
DVB-S2X LDPC/BCH Decoder
DVB-S2X is the next generation satellite transmission standard that extends its well-established predecessor DVB-S2. The new specification allows for ...
229
1.0
DVB-S2X Modulator
The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...
230
1.0
DVB-S2X Multi-Carrier Demodulator
The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel....
231
1.0
DVB-S2X Wideband Demodulator
The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 ...
232
1.0
DVB-S2X Wideband LDPC/ BCH Decoder
The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs...
233
1.0
DVB-S2X Wideband Modulator
The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...
234
0.3729
A bridge to convert the slave SPI interface to the master I2C interface and vice versa
The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....
235
0.3729
A bridge to convert the slave SPI interface to the master UART interface and vice versa
The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....
236
0.118
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature....
237
0.118
10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....
238
0.118
10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process
10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process....
239
0.118
10/100 Ethernet PHY IP, UMC 0.18um MS process
10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process....
240
0.118
10/100 Ethernet PHY IP, UMC 65nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process....
241
0.118
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process....
242
0.118
10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_
10/100/1000 ETHERNET CONTROLLER WITH AHB AND AXI BUS...
243
0.118
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
244
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process...
245
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
246
0.118
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process...
247
0.118
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....
248
0.118
Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP
10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....
249
0.118
Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
10/100/1000 Ethernet Controller with AHB bus....
250
0.0
4-channel ATSC 8VSB Modulator
The IPrium-ATSC-8VSB-Modulator IP Core implements the USA DTV standard ATSC A/53 Part 2. The IP Core contains Scrambler, RS Encoder, Trellis Encoder, ...