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417 IP
251
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D-MAC-10/100
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...
252
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2.5G BaseT Ethernet PHY IP in TSMC 22ULL
The 2.5G BaseT Ethernet PHY IP Core provides a robust, production-proven physical layer solution for SoCs requiring high-speed, low-power Ethernet con...
253
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2.5G BaseT Ethernet PHY IP in TSMC 28HPC+
The 2.5G BaseT Ethernet PHY IP built on the 28nm process delivers a cost-effective and performance-optimized physical layer solution for a broad spect...
254
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1.6T Ethernet MAC Controller IP
The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simp...
255
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G.9960 LDPC Decoder
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in th...
256
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5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency. It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G ope...
257
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10/100/1000 MBit Ethernet MAC
The GigaBit Ethernet Media Access Controller (GRETH_GBIT) supports 10/100/1000 MBit speed in both full- and half-duplex operation. The dataflow is han...
258
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10/25/40/100G Ethernet MAC
The Chevin Technology Ethernet MAC IP core can simplify the FPGA integration of Ultra low-latency 10/25/40/100G MAC Ethernet connectivity in Intel and...
259
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10/25/40/100G Ethernet PCS/PMA
The Chevin Technology PCS/ PMA is an IP core that simplifies the FPGA integration of Ultra low-latency 10/25/40/100G Ethernet connectivity in Intel an...
260
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10/25/40/100G MAC/PCS Ethernet IP Core
The 10/25/40/100G MAC IP core is a Low-Latency Ethernet MAC with a latency of 44.8ns in 2749 LUTs for 10Gbit/s and 20.5ns in 2680 LUTs for 25Gbit/s. W...
261
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100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm with fully-parallel and ...
262
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100G Ethernet PCS IP
The Synopsys 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable ...
263
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100M-1000M BaseT1 Ethernet PHY IP in TSMC 22ULL
The 100M/1000M Base-T1 Ethernet PHY IP Core provides single-pair Ethernet connectivity with full IEEE 802.3bw and 802.3bp compliance, enabling reliabl...
264
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100M/1000M Base-T1 Ethernet PHY IP in TSMC 28HPC+
The 100M/1000M Base-T1 Ethernet PHY IP Core delivers single-pair Ethernet connectivity with full IEEE compliance in a 28nm process node. Supporting bo...
265
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10Base-T/100Base-TX/1000Base-T Gigabit Ethernet PHY IP （GPHY） in TSMC40
Provides Gbit Ethernet PHY that supports 10M/100M/1000M Base-T and can be applied in Ethernet related scenarios. It can be independently taped out, su...
266
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10G Base T Ethernet PHY
Terminus Circuits presents a state-of-the-art Ethernet PHY IP, supporting 100 Mbps, 1 Gbps, and 10 Gbps data rates. Purpose-built for performance-driv...
267
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10G Ethernet PHY IP In SAMSUNG 14LPP
The 10G Ethernet PHY IP Core, designed in 14nm FinFET technology, enables next-generation high-speed connectivity with full compliance to IEEE 802.3 E...
268
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10G I.3 BCH Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward error correction algorit...
269
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40G I.3 BCH Encoder/Decoder for ITU G.975.1
The IPrium-40G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward error correction algorit...
270
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10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and is fully compatible ...
271
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40G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-40G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and is fully compatible ...
272
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10G I.9 BCH Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.9-BCH-Codec IP core implements "two interleaved extended BCH" super-FEC code for optical lines and is fully compatible with ITU-T G.9...
273
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40G UDP IP Stack
Logic Fruit’s 40G UDP IP Stack implements a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connection or LAN....
274
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10G UDP IP Stack
This 10G UDP IP Stack carries out the implementation of a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connec...
275
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10G/40G RS(255,239) Encoder/Decoder for ITU G.709
The IPrium-10G-G.709-Codec IP Core implements the error-correcting coding Reed-Solomon (255, 239) for the ITU-T G.709 recommendation. Supports synchro...
276
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10Gbit/s Ethernet UDT Server for FPGAs
FPGA Synthesisable 10Gbit/s Ethernet UDT4 server for reliable long distance/high bandwidth data transfer...
277
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112G Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
278
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112G Ethernet PHY for VSR on TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
279
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112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
280
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112G Ethernet PHY IP LR-Max for TSMC N4P
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
281
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112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
282
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112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
283
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112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
284
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32-channel 64-QAM/256-QAM J.83 Annex B Cable Modulator
The IPrium-J83B-C-Modulator IP Core is 32-channel J.83B Modualtor with MAX5861 (MAX5862) support....
285
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32-channel DVB-C Modulator
The IPrium-DVB-C-Modulator IP Core is 32-channel DVB-C Modualtor with MAX5861 (MAX5862) support....
286
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320Gbps Ethernet Switch
Packet Architects offers a series of high speed switching IPs which are developed using the unique FlexSwitch toolchain. The toolchain allows a fast a...
287
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224G Ethernet PHY for TSMC 3nm
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
288
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224G Ethernet PHY IP for TSMC N3E
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
289
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25G LL MAC /PCS Ethernet IP for FPGA
The Chevin Technology 25G LL MAC/PCS combines the 25G MAC and 25G PCS IP cores to obtain the lowest possible latency while simplifying the integration...
290
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25Gbit/s Ethernet MAC
The Chevin Technology 25GMAC IP core provides Ultra Low-Latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. The 25GMAC can...
291
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25Gbit/s Ethernet PCS
The Chevin Technology 25GPCS provides Ultra low-latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. Ultra-low latency is achie...
292
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16G Ethernet SerDes PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
293
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MAC - DMAC - 10/100 Mb Media Access Controller
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...
294
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UALink DL
he Chip Interfaces UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cati...
295
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UALink TL
The Chip Interfaces UA Link TL IP Core is a high-performance, silicon-agnostic and fully compliant Transaction Layer implementation of UALink_200 spec...
296
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Hamming Code ECC
The RTL is configurable for number of message bits that need ECC protection. Once RTL is generated it is fixed. 1- RTL has no RAMS/ROMS/Flip Flop...
297
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Manchester Encoder / Decoder
The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code and vice-versa. The ...
298
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Fast Ethernet 10/100 802.3 MAC with IEEE 1588 PTP Support
The Arasan 10/100 Ethernet Media Access Controller with IEEE 1588 support IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. It also inclu...
299
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Fast Ethernet 802.3 Media Access Controller (MAC)
The Arasan 10/100 Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The 10/100 Ethern...
300
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Fast Fourier Transform IP Core
The Creonic Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FF...