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433 IP
301
1.0
DVB-S2X Wideband LDPC/ BCH Decoder
The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs...
302
1.0
DVB-S2X Wideband Modulator
The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...
303
0.3729
A bridge to convert the slave SPI interface to the master I2C interface and vice versa
The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....
304
0.3729
A bridge to convert the slave SPI interface to the master UART interface and vice versa
The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....
305
0.118
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature.
0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature....
306
0.118
10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....
307
0.118
10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process
10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process....
308
0.118
10/100 Ethernet PHY IP, UMC 0.18um MS process
10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process....
309
0.118
10/100 Ethernet PHY IP, UMC 65nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process....
310
0.118
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process....
311
0.118
10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_
10/100/1000 ETHERNET CONTROLLER WITH AHB AND AXI BUS...
312
0.118
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
313
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process...
314
0.118
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...
315
0.118
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process...
316
0.118
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....
317
0.118
Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP
10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....
318
0.118
Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
10/100/1000 Ethernet Controller with AHB bus....
319
0.0
D-MAC-10/100
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...
320
0.0
1.25 Gbps EPON SerDes IP
The MXL-SRDS-EPON is an Ethernet Passive Optical Network (EPON) transceiver implemented in digital CMOS technology. The SerDes IP offers data transfer...
321
0.0
G.9960 LDPC Decoder
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in th...
322
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency. It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G oper...
323
0.0
10/100 Mb Media Access Controller
Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...
324
0.0
100G Ethernet PCS IP
The Synopsys 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable ...
325
0.0
10G Base T Ethernet PHY
Terminus Circuits presents a state-of-the-art Ethernet PHY IP, supporting 100 Mbps, 1 Gbps, and 10 Gbps data rates. Purpose-built for performance-driv...
326
0.0
10Gbit/s Ethernet UDT Server for FPGAs
FPGA Synthesisable 10Gbit/s Ethernet UDT4 server for reliable long distance/high bandwidth data transfer...
327
0.0
112G Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
328
0.0
112G Ethernet PHY for VSR on TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
329
0.0
112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
330
0.0
112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
331
0.0
112G Ethernet PHY IP LR-Max for TSMC N4P
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
332
0.0
112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
333
0.0
112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
334
0.0
112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...
335
0.0
320Gbps Ethernet Switch
Packet Architects offers a series of high speed switching IPs which are developed using the unique FlexSwitch toolchain. The toolchain allows a fast a...
336
0.0
224G Ethernet PHY for TSMC 3nm
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
337
0.0
224G Ethernet PHY IP for TSMC N3E
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
338
0.0
25G LL MAC /PCS Ethernet IP for FPGA
The Chevin Technology 25G LL MAC/PCS combines the 25G MAC and 25G PCS IP cores to obtain the lowest possible latency while simplifying the integration...
339
0.0
25Gbit/s Ethernet MAC
The Chevin Technology 25GMAC IP core provides Ultra Low-Latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. The 25GMAC can...
340
0.0
25Gbit/s Ethernet PCS
The Chevin Technology 25GPCS provides Ultra low-latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. Ultra-low latency is achie...
341
0.0
16G Ethernet SerDes PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
342
0.0
UALink IP Solution with PHY, Controller and Verification IP
The Synopsys UALink IP solution, consisting of UALink Controller, PHY, and verification IP, is designed to meet the performance requirements for AI Ac...
343
0.0
Manchester Encoder / Decoder
The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code and vice-versa. The ...
344
0.0
Fast Fourier Transform IP Core
The Creonic Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FF...
345
0.0
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC
Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE...
346
0.0
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP
An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX operation is known as...
347
0.0
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications. It can operate in 10BASE-T, 100BASE-TX, ...
348
0.0
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF
The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption. It is capable of operating in 1...
349
0.0
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+
For Gigabit 10/100/1000 Ethernet applications, the GPHY is a highly integrated single chip. It is a singleport, IEEE 802.3u/ab compatible, power effic...
350
0.0
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption. It is capable of functioning in 10BASE-T, ...