Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow CEI (10)
arrow Cell / Packet (6)
arrow Error Correction/Detection (152)
arrow Ethernet (167)
arrow Fibre Channel (1)
arrow HDLC (6)
arrow Interleaver/Deinterleaver (1)
arrow Modulation/Demodulation (22)
arrow Optical/Telecom (36)
arrow Other (13)
414 IP
351
0.0
WiMAX IEEE802.16e Transceiver IP Core
The transceiver is designed to be used together with an RF tuner and ADC/ DAC converters. The system has internal state machine to control the operat...
352
0.0
Single Channel HDLC Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Pri...
353
0.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....
354
0.0
Viterbi Decoder
Viterbi decoders are commonly used to decode convolutional codes in communications systems. This Viterbi Decoder is a fully parallel implementation wh...
355
0.0
Viterbi Decoder
The IPrium-Viterbi-Decoder IP Core implements Viterbi decoding algorithm and supports trellis mode of operattion....
356
0.0
Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...
357
0.0
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one it...
358
0.0
Ultra Ethernet MAC & PCS 100G/200G/400G/800G
The Chip Interfaces Ultra Ethernet MAC & PCS IP core delivers a complete, silicon-agnostic implementation of the Ultra Ethernet Transport link layer, ...
359
0.0
eMAC Gigabit Ethernet MAC Media Access Controller
Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. The controller pro...
360
0.0
Industry's first complete L1+L2 Ethernet IP solution for AI scale-up networks, aligned to OCP ESUN 1.0 spec
The Synopsys Ethernet for Scale-Up Networking (ESUN) IP solution, is the industry’s first complete Layer 1 and Layer 2 IP offering purpose-built for E...
361
0.0
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier. Transmit and receive part ...
362
0.0
Polar Encoder / Decoder for 3GPP 5G NR
Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy...
363
0.0
Nonbinary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
364
0.0
SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
The IPrium-SOQPSK-LDPC-Modulator IP Core implements constant amplitude CPM SOQPSK modulation with LDPC Coding. The IP Core is a complete digital SOQPS...
365
0.0
Low-Latency 10/100/1000 Ethernet MAC
The LLEMAC-1G implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Feat...
366
0.0
Low-Latency IP 10G Ethernet MAC
LeWiz makes available its ultra low-latency 10G Ethernet MAC for IP licensing - targeting low-latency applications such as those in the financial sect...
367
0.0
APB Pulse Width Modulator
The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal. The frequency of the output waveform is eithe...
368
0.0
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference f...
369
0.0
ARP/ICMP Protocol for Ethernet
The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...
370
0.0
RS-QPSK Modem with low latency
The IPrium-RS-QPSK Modem IP Core is a complete BPSK/QPSK modem with integrated Reed-Solomon Forward Error Correction (FEC) and is optimized for extrem...
371
0.0
ISDB-S3-LDPC-BCH Decoder IP
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...
372
0.0
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending...
373
0.0
FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clo...
374
0.0
QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial cloc...
375
0.0
QSPI Whitebox IP
This SPI/DSPI/QSPI Controller IP supports single-, dual-, and quad-data-line serial transfers for Flash memory and general-purpose peripherals. Its pr...
376
0.0
USXGMII Ethernet PCS (PCSR_X)
The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any syst The Cadence USXGMI...
377
0.0
LTE Turbo Decoder
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the interna...
378
0.0
Ethernet 10/100 MAC (Exclusively for Turnkey ASIC design; not for standalone licensing)
The Ethernet controller is compliant with IEEE802.3 and it provides an interface between the host subsystem and the Media Independent Interface (MII)....
379
0.0
Ethernet 100G PCS IP
SmartDV's Ethernet 100G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable,...
380
0.0
ETHERNET 10G MAC
The 10G Ethernet MAC core is a thoroughly verified Ethernet Media Access Controller function that interfaces with physical layer devices in an Etherne...
381
0.0
Ethernet 10G PCS IP
SmartDV's Ethernet 10G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable 1...
382
0.0
Ethernet 10M/100M/1G PCS IP
SmartDV's Ethernet 10M/100M/1G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring fl...
383
0.0
Ethernet 2.5G PCS IP
SmartDV's Ethernet 2.5G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring 2.5 Gigab...
384
0.0
Ethernet 200G PCS IP
SmartDV's Ethernet 200G PCS IP is an FPGA-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring high-bandwi...
385
0.0
Ethernet 25G PCS IP
SmartDV's Ethernet 25G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable, ...
386
0.0
Ethernet 40G PCS IP
SmartDV's Ethernet 40G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable 4...
387
0.0
Ethernet 50G PCS IP
SmartDV's Ethernet 50G PCS IP is a silicon-proven, fully featured Physical Coding Sublayer solution purpose-built for SoC designs requiring reliable, ...
388
0.0
Ethernet Cyclic FEC IP
SmartDV's Ethernet Cyclic FEC IP is a silicon-proven, fully featured Forward Error Correction solution purpose-built for SoC designs requiring reliabl...
389
0.0
Ethernet L2 Switch IP
SmartDV's Ethernet L2 Switch IP is a silicon-proven, fully featured Layer 2 Ethernet switch solution purpose-built for SoC designs requiring flexible,...
390
0.0
Ethernet MAC 100G/200G/400G/800G/1.6T
The Chip Interfaces 100G/200G/400G/800/1.6T Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementin...
391
0.0
Ethernet PCS 100G/200G/400G/800G/1.6T
Chip Interfaces 100G-1.6T Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet st...
392
0.0
Ethernet Tri-Speed MAC (10M/100M/1G) IP
SmartDV's Ethernet Tri-Speed MAC IP is a silicon-proven, fully featured Media Access Controller solution purpose-built for SoC designs requiring flexi...
393
0.0
Ethernet XAUI PCS
Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the logic required to ...
394
0.0
Automotive Ethernet (100BaseT1) Whitebox PHY IP with BroadR Reach
The Automotive Ethernet PHY IP Core is a 100M Ethernet PHY IP. Boasting a BroadR-Reach™ feature compatible with 100BaseT1 operations. It is a highly i...
395
0.0
Automotive Ethernet Whitebox PHY IP - ST 28FDSOI
The Automotive Ethernet PHY IP Core is a 100M Ethernet PHY IP. Boasting a BroadR-Reach™ feature compatible with 100BaseT1 operations. It is a highly i...
396
0.0
AVB MAC IP
SmartDV's AVB MAC IP is a silicon-proven, fully featured Audio Video Bridging Ethernet MAC solution purpose-built for SoC designs requiring determinis...
397
0.0
DVB-C Demodulator IP Core
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine ...
398
0.0
DVB-C2 LDPC Decoder IP
The Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...
399
0.0
DVB-C2 LDPC/ BCH Decoder IP Core
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes co...
400
0.0
DVB-S2 LDPC Decoder IP
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...