Design & Reuse
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arrow Other (38)
433 IP
351
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ECDSA sign engine
Elliptic curves form the foundation of cutting-edge public-key cryptography, serving as a crucial component for secure digital signatures and robust k...
352
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ECDSA sign engine
When safety & security meet the best size/performance ratio… ECDSA IP Core Elliptic curves form the foundation of cutting-edge public-key cryptograph...
353
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ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital Signature Algorithm ...
354
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ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital Signature Algorithm ...
355
0.0
BCH Decoder IP
The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about p...
356
0.0
NCR Processor
NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...
357
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CCSDS 8160/ 7136 Decoder and Encoder
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358
0.0
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain h...
359
0.0
CCSDS SCCC Modulator/ Turbo Encoder
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360
0.0
Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support
Octal SPI master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Macronix (MX66LM1G45G) Octal SPI REV.1.0 sp...
361
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
362
0.0
LDPC Decoder IS-GPS-800D IP
The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...
363
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Reed Solomon
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...
364
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Reed Solomon Decoder and Encoder FEC IP Core
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...
365
0.0
Centralized Network Configurator (CNC) for TSN nodes such as endpoints and Switches
Centralized Network Configurator or CNC is a component used in Time Sensitive Networking (TSN) networks. The CNC monitors data streams while coordinat...
366
0.0
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interfa...
367
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Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding. The serializer (except 32 bit inputs...
368
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
369
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Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32. The serializer (except 32 bit outputs) is implemented b...
370
0.0
Networking SerDes IP, Silicon Proven in ST 28FDSOI
The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical...
371
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AFDX 1G MAC IP
AFDX 1G MAC core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet IEEE standards ,ARINC 664 and supports 10/100/10...
372
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5G-NR LDPC Encoder
The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high th...
373
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1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching IP cores, developed using the unique FlexSwitch toolchain. This toolchain provides a fast an...
374
0.0
Gigabit Ethernet 802.3 MAC Controller IP
The Giga MAC IP is an embedded Fast Ethernet controller module. It is compliant with IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE802....
375
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Gigabit Ethernet Media Access Controller
Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. The controller pro...
376
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High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
377
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high-performance solution for elliptic curve cryptography
Our ECC IP Core represents a cutting-edge solution that brings the power of elliptic curve cryptography to your systems. Designed with versatility and...
378
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WiMAX IEEE802.16e Transceiver IP Core
The transceiver is designed to be used together with an RF tuner and ADC/ DAC converters. The system has internal state machine to control the operat...
379
0.0
Single Channel HDLC Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Pri...
380
0.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....
381
0.0
Flash Memory LDPC
LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...
382
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Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one it...
383
0.0
eMMC LDPC Encoder/Decoder
Mobiveil’s eMMC LDPC Encoder/Decoder is an advanced flash reliability solution engineered to maximize flash endurance and retention. Featuring industr...
384
0.0
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier. Transmit and receive part ...
385
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Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing
Secure-IC provides integrated Secure Elements (iSE) that can act as trust anchors to protect the security assets of a device. An iSE - also referred a...
386
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Nonbinary LDPC Decoder
A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...
387
0.0
Doppler Channel IP Core
The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...
388
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Low-Latency 10/100/1000 Ethernet MAC
The LLEMAC-1G implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Feat...
389
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APB Pulse Width Modulator
The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal. The frequency of the output waveform is eithe...
390
0.0
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference f...
391
0.0
ARP/ICMP Protocol for Ethernet
The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...
392
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ISDB-S3-LDPC-BCH Decoder IP
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...
393
0.0
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending...
394
0.0
FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clo...
395
0.0
QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial cloc...
396
0.0
eSPI Slave SOC IP
eSPI Slave SOC is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSPI...
397
0.0
LTE Turbo Decoder
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the interna...
398
0.0
ETHERNET 100G MAC IP
Ethernet 100G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple int...
399
0.0
ETHERNET 100G PCS IP
Ethernet 100G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple int...
400
0.0
ETHERNET 10G KR PCS IP
Ethernet 10G KR PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple i...