Design & Reuse
Catalog of SIP Cores
System on Chip design resources
4 IP
1
30.0
NPU IP for Advanced Video Processing: Introducing WAVE-N for AI ISP, SR, NR, Demosaic, OD, and Segmentation
WAVE-N is a high-performance, video-specialized NPU IP designed to deliver real-time, deep learning-based image enhancement for edge devices. By utili...
2
6.0
Machine Learning Accelerator, NPU
CSEM’s machine learning (ML) platform is built around the Fibonacci ML System-on-Chip (SoC) — a hierarchically scalable architecture inspired by the F...
3
6.0
Flexible Low-Power AI/ML Accelerator for Time Series Signals
FETA is a standalone, low-power hardware accelerator developed by CSEM for executing AI/ML workloads—especially Recurrent Neural Networks (RNNs)—on ti...
4
6.0
ML Accelerator MFCC Feature Extractor 22nm
The MFCC (Mel-Frequency Cepstrum Coefficients) core block is a high-efficiency feature extractor for voice signals, compliant with ETSI ES 201 108 sta...