Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Emulation (5)
arrow Monitoring and Debugging (13)
arrow Prototyping (10)
arrow Simulation and Verification (27)
27 IP
1
80.0
Meridian CDC Clock Domain Crossing Sign-Off
Meridian CDC (Clock Domain Crossing) is the fastest, highest capacity and most precise clock domain crossing tool in the market for CDC sign-off. Its ...
2
80.0
Meridian RDC Reset Domain Crossing Sign-Off
Meridian RDC (Reset Domain Crossing) provides comprehensive sign-off for reset domain crossing (RDC) to prevent metastability, reset glitches, and rec...
3
50.0
SafeConnect Connectivity & Glitch Sign-Off
SafeConnect enables comprehensive connectivity checks and glitch sign-off at both RTL and netlist stages. Using high-capacity static analysis, it dete...
4
50.0
Meridian DFT Multimode Design for Testability Sign-Off
Meridian DFT (Design For Test) from Real Intent delivers multimode design-for-test (DFT) static sign-off to ensure maximum scan coverage and silicon s...
5
50.0
Conquest Sentry Hardware Security Sign-Off
Sentry is a high-capacity hardware security static sign-off solution that verifies data integrity, leakage prevention, and interference safeguarding a...
6
10.0
DesignWare Library contains the essential infrastructure IP for design and verification
The DesignWare Library contains the essential infrastructure IP for design and verification including datapath components, AMBA On-Chip Bus and microc...
7
3.0
Fault Injection Studio
FortifyIQ’s Fault Injection Studio enables engineers to evaluate and strengthen hardware designs against fault injection attacks, e.g., DFA, SIFA, and...
8
3.0
Side Channel Studio
FortifyIQ's FortifEDA Side-Channel Studio Analyzes leakage vulnerabilities throughout design flow by generating simulated power traces, performing st...
9
0.7246
TileLink VIP
TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC. The SmartDV s TileLink Verification IP is fully co...
10
0.7246
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other ...
11
0.7246
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces. It includes an e...
12
0.0
A UVM‑compatible audio_dmic virtual IP (VIP)
A UVM‑compatible audio_dmic virtual IP (VIP) that enables fast, accurate verification of digital microphone interfaces by emulating real‑world PDM aud...
13
0.0
A UVM‑compatible audio_fft virtual IP (VIP)
A UVM‑compatible audio_fft virtual IP (VIP) that streamlines verification of FFT‑based audio processing by generating, monitoring, and validating spec...
14
0.0
A UVM‑compatible audio_if virtual IP (VIP)
A UVM‑compatible audio_if virtual IP (VIP) that accelerates verification of digital parallel and I2S interfaces by accurately modeling interface behav...
15
0.0
Path Margin Monitor IP
The Path Margin Monitor (PMM) solution consists of multiple PMM units, a PMM controller, and associated software & EDA automation. PMM IP is a buildin...
16
0.0
VC Functional Safety Manager
VC Functional Safety Manager provides a comprehensive tool for IP and semiconductor groups targeting functional safety certification for ISO 26262, IE...
17
0.0
IEEE 1149.7 Compact TAP
The IEEE 1149.7 Compact TAP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE 1149.7 featu...
18
0.0
Mem Test Analyzer Core
The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core. The Mem Test Analyzer Core can be used in ...
19
0.0
Performance modeling using stochastic components
Evaluate The System Architecture And Generate Latency/Throughput Graphs. In stochastic modeling, different channels need to be modeled for each input-...
20
0.0
Tessent Embedded SDK
The Tessent Embedded Software Development Kit (ESDK) is a set of software libraries designed to be compiled and run on an embedded system within an So...
21
0.0
Analog FastSPICE Platform
Foundry-certified, the AFS Platform delivers nm SPICE accuracy >5x faster than traditional SPICE and >2x faster than parallel SPICE simulators. Offeri...
22
0.0
OneSpin - Certified IC Integrity Solutions to Develop Functionally Correct, Safe, Secure, and Trusted Integrated Circuits
OneSpin provides the most advanced and robust verification platform to address today s critical IC integrity issues. Our experts are dedicated to solv...
23
0.0
STAR Hierarchical System (SHS) IP
Synopsys SLM STAR Hierarchical System (SHS) is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores...
24
0.0
STAR Memory System (SMS) Test & Repair IP
Synopsys SLM SMS IP is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories ...
25
0.0
STAR Memory System (SMS) Test & Repair IP for CAMs (Content Addressable Memories)
Synopsys SLM SMS CAM 6 IP can be used to perform Test, Repair and Diagnostics for Content Addressable Memories such as BCAM, TCAM, XYCAM...
26
0.0
Multi-domain simulation at the system-level for mixed signal behavior modeling
The simulators implement various models of computation. Most of these models of computation can be viewed as a framework for component-based design, w...
27
0.0
Symphony Mixed-Signal Platform
The industry s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across A/D...