1 5.0556

A TSMC 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications. The IO operates at either 1.8V or 3.3V and can dynamically sw...

2 5.0556

A radiation-hardened TSMC 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell Key attributes of the 130nm IO library include an extended operational temperature range (-55°C to 200°C), sleep retention, and a built-in power regul...

3 4.0556

RGMII I/O offerings Certus is pleased to offer Reduced Gigabit Media Independent Interface (RGMII) compliant IOs in advanced technology nodes. The Certus solutions suppo...

4 4.0556

Secure Digital I/O offerings Certus is pleased to offer Secure Digital compliant IOs in advanced technology nodes. Our SD IOs support DS, HS, SDR25, SDR50, DDR50 and SDR104 prot...

5 0.0

Bi-Directional LVDS with LVCMOS BiDirectional LVDS IO circuit combines LVDS driver and receiver circuits to enable a single pair of IO pads to function as a 1.5Gbps bi-directional LV...

6 0.0

Wide-range LVDS Video Interface Flexible video deserializer capable of receiving 18bit, 24bit, and 30bit video data with embedded sync and control carried over four or five serial LV...

7 0.0

LVDS Transmitter The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and high data rates. The...

8 0.0

LVDS Receiver The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and high data rates. The d...

9 1.0

Sub-LVDS receiver followed by 1:4 de-serializer The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word. The receiver defined in this IP is ...

10 1.0

32:1 serializer followed by sub-LVDS drivers The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in s...

11 1.0

LVDS receiver, 650M, 5 channel The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

12 1.0

650M LVDS transmitter, 5 channel The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

13 1.0

SMIC 0.13um LVDS Receiver The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

14 1.0

SMIC 0.13um LVDS Transmitter The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream ...

15 1.0

SMIC 0.18um LVDS Transceiver The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial stream. This single s...

16 1.0

IBM 65nm LVDS Transmitter The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

17 1.0

IBM 65nm LVDS Receiver The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Sin...

18 1.0

IBM 65nm LVDS Transmitter The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream ...

19 1.0

IBM 65nm Mini-LVDS Transmitter The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link transmission with up to ...

20 1.0

SMIC 65nm Low Leakage LVDS Receiver The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Sin...

21 1.0

TSMC 0.13um LVDS Transmitter The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

22 0.0

1 Gbps DDR LVDS transmitter 065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other ...

23 0.0

1 Gbps DDR rail to rail LVDS receiver LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data a...

24 0.0

2.4 Gbps LVDS transmitter 065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin...

25 0.0

1 Gbps Rail to Rail LVDS receiver 065TSMC_LVDS_08 is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTP, OUTN) to receiv...

26 1.0

Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver ...

27 1.0

Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter ...

28 20.0

NVM FTP Trim in SMIC (180nm, 110nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

29 20.0

NVM FTP Trim in TowerJazz (180nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

30 3.0

12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V) SESAME BiV 40 uLP a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use of...

31 2.0

ONFI 4.1 I/O Pad Set The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to supp...

32 2.0

3.3V 100MHz Oscillator I/O Pad Set The 3.3V 100MHz Oscillators library includes a programmable oscillator macro I/O cell. ▪ 100 MHz programmable oscillator These libraries are off...

33 2.0

1.8V 3.3V Tolerant General Purpose IO The 1.8V GPIO 3VT library provides general purpose bidirectional I/O cells that are both fault tolerant and 3.3V tolerant. These programmable, multi-v...

34 2.0

CI Plus The CI Plus library provides a programmable bi-directional I/O cell designed to meet the signal interface requirements of the Common Interface. This l...

35 2.0

3.3V Wide-Range General Purpose Staggered I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

36 2.0

1.8V General Purpose I/O Inline Pad Set The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

37 2.0

3.3V Wide-Range General Purpose I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

38 2.0

subLVDS I/O Pad Set The subLVDS library provides a subLVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data...

39 2.0

SSTL_15 / SSTL_18 Combo I/O Pad Set The SSTL_15_18 combo pad set supports bidirectional single-ended and differential SSTL_15 and SSTL_18 signaling. The driver/receiver pairs, with embe...

40 2.0

SSTL_15 IO Pad Set The SSTL_15 pad set supports bidirectional single-ended and differential SSTL_15 signaling. The driver/receiver pairs, with embedded power cells, ar...

41 3.0

12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V) SESAME BiV 40 uLPeFlash a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...

42 2.0

3.3V 32 KHz RTC and Programmable 100MHz Oscillator I/O Pad Set The Oscillator library provides oscillators for on-chip asynchronous clock generation with an appropriate external crystal. This library is provided...

43 2.0

LVDS I/O Pad Set The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rate...

44 2.0

1.8V GPIO: 3.3V Tolerant The 1.8V Fault-Tolerant General Purpose I/O library provides a 3.3V tolerant programmable, bidirectional I/O that give the system designer the flexibi...

45 2.0

ICC I/O Pad Set The ICC library provides the bidirectional reset, clock, and data I/O drivers for the smart card UICC terminal interface. This library has been desi...

46 2.0

3.3V Wide-Range General Purpose I/O Pad Set The 3.3V General Purpose I/O library provides bidirectional I/O, analog I/O, and a full complement of I/O power, core power, and analog power cells al...

47 2.0

2.5V Wide-Range General Purpose I/O Pad Set The 2.5V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spa...

48 2.0

5V Programmable GPIO The 5V General Purpose I/O libraries provide bidirectional I/O, analog I/O, and a full complement of I/O power, core power, and analog power cells alo...

49 2.0

RF I/O Pad Set and Discrete RF ESD Protection Components The RF libraries include analog signal pads and ESD protection components for RF applications. These libraries are offered as a supplement to the stan...

50 2.0

USB 2.0 OTG ESD Protection I/O Pad Set The USB 2.0 OTG ESD Protection library provides a comprehensive ESD solution for USB 2.0 hard macro cells....