1601 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

1602 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1603 0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell. UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....

1604 0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell. UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....

1605 0.0

Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range up to 80 k...

1606 2.0

PCI IO Pad Set The PCI 3.0 library provides the driver / receiver and required support cells for PCI 3.0 signaling. The cells are compliant with the PCI Local Bus S...

1607 0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1608 0.118

UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library...

1609 0.118

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library...

1610 0.118

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library...

1611 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1612 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1613 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1614 0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1615 0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1616 0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1617 2.0

RGMII IO Pad Set The (R)GMII library provides the combo driver / receiver and required support cells for (R)GMII signaling. The libraries are compliant with the Gigabi...

1618 0.118

UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library...

1619 0.118

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...

1620 0.118

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library...

1621 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....

1622 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...

1623 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

1624 0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

1625 0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

1626 0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

1627 0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

1628 2.0

SD 3.0 I/O Pad Set The SD library provides the driver / receiver cell and required support cells for SD 3.0 signaling. Fault-tolerant operation. This library is offere...

1629 0.118

UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1630 0.118

UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1631 0.118

UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library...

1632 0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1633 0.118

UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1634 0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1635 0.118

UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35) UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)...

1636 0.118

UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35) UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)...

1637 0.118

UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm) UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)...

1638 0.118

UMC 0.18um Generic process MPCA core cell library UMC 0.18um Generic process MPCA core cell library...

1639 2.0

SSTL_15 IO Pad Set The SSTL_15 library supports bidirectional single-ended and differential SSTL_15 signaling. The driver/receiver pairs, with embedded power cells, are...

1640 0.118

UMC 90nm LL/RVT MPCA core cell library UMC 90nm LL/RVT MPCA core cell library...

1641 0.118

UMC 65nm SP/RVT Logic Process MPCA cell library UMC 65nm SP/RVT Logic Process MPCA cell library...

1642 0.118

UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming...

1643 0.118

UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4 UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4...

1644 0.118

UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming...

1645 0.118

UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler...

1646 0.118

UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT...

1647 0.118

UMC 28HPM UHS 1PRF UMC 28HPM UHS 1PRF...

1648 0.118

UMC 28nm HPM ultra high speed register compiler UMC 28nm HPM ultra high speed register compiler...

1649 0.118

UMC 40nm Low Power Process One Port Register File wit 213 cell UMC 40nm Low Power Process One Port Register File wit 213 cell...

1650 2.0

subLVDS IO Pad Set The subLVDS library provides an subLVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data ...