Design & Reuse
2807 IP
2801
0.0
Stallable 1toN Expansion Pipeline Register
This block is used as a width expander as part of a processing pipeline. It may receive multiple(N) input words, concatenate them and present them fo...
2802
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
2803
0.0
Stallable Nto1 Contraction Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the rat...
2804
0.0
Stallable Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully comp...
2805
0.0
Zero fall-through synchronous FIFO
Fully synchronous FIFO with zero fall-through such that when empty the FIFO behaves like a single stage register....
2806
6.0
Single- and double-precision IEEE-754 floating-point unit
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu...
2807
2.2581
40Mbps LVDS IO
40Mbps LVDS IO...