Design & Reuse
Catalog of SIP Cores
System on Chip design resources
2828 IP
2801
1.0
Sine Function
Function y = sin(x) calculates the sine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic c...
2802
2.0
Pipelined Multiplier
Function y = a * b is a high-speed multiplier with configurable width and depth. Inputs and outputs may be specified as either signed or unsigned val...
2803
2.0
Pipelined Divider
Function y = a / b is a very high-speed divider with configurable dividend and divisor width. Inputs and outputs may be specified as either signed or...
2804
2.0
Pipelined Square Root
Function y = √x is a fully scalable square-root function with configurable data width. Inputs and outputs are unsigned integers. An n-bit input valu...
2805
2.0
4-Quadrant Arctan Function
Function φ = atan2(y,x) calculates the 4-quadrant inverse tangent in the range -Pi to Pi. Functionally equivalent to the atan2 function in 'C' an...
2806
1.0
SinCos Function
Function calculates the Sine and Cosine of input x in radians. Inputs are 18-bit signed values in the range -Pi to Pi. Output values are 17-bit sign...
2807
2.0
Arctan Function
Function y = atan(x) calculates the inverse tangent of a fraction. It has a high-speed, fully pipelined architecture and uses a polynomial with dynam...
2808
0.0
Floating point multiplier
Floating point multiplier...
2809
0.0
Floating point MAC
Floating point MAC...
2810
4.0556
5V ESD Clamp in GlobalFoundries 180nm LPe
5V, ESD clamp in GlobalFoundries 180nm that can be used for either signal protection or 1.8V Power supplies. The clamp is a compact single cell, 44um ...
2811
0.0
GPIO IP
GPIO provides general purpose input output interface with AXI, AHB, Avalon and APB, compatible with standard protocol of GPIO specifications. Through ...
2812
4.0556
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V SLVS Transceiver
This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology. D...
2813
0.0
DolphinWare Arithmetic Components Ips
Dolphin Technology provides DolphinWare Arithmetic Components IPs, consist of Math Operators and Converters....
2814
0.0
DolphinWare Control Logic Ips
Dolphin Technology provides DolphinWare Control Logic IPs, consist of Arbiter and FIFO....
2815
0.0
DolphinWare Data Integrity Ips
Dolphin Technology provides DolphinWare Data Integrity IPs, consist of Encoders, Decoders and Error Correction....
2816
10.0
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating point (FP) components th...
2817
0.0
Asynchronous FIFO with flags and depth counter
...
2818
0.0
IEEE 754 Floating Point Coprocessor
The A2F3 is a fully synthesizable module implemented in Verilog RTL. It is a co-processor unit providing floating-point computation compliant with th...
2819
0.0
Half Precision IEEE-754R complete FPU for graphics processing
This block may be used to convert and existing single register stage into a stallable pipeline stage. It can also be used with synchronous RAM blocks...
2820
0.0
Queue Structure
The A2Q implements hardware queues for use as FIFOs and LIFOs for inter-process communications, especially in real-time applications. They can be us...
2821
0.0
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The b...
2822
0.0
Stallable 1toN Expansion Pipeline Register
This block is used as a width expander as part of a processing pipeline. It may receive multiple(N) input words, concatenate them and present them fo...
2823
0.0
Asynchronous FIFO alternate design
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domain...
2824
0.0
Stallable Nto1 Contraction Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. A parameter defines the rat...
2825
0.0
Stallable Pipeline Register
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built. The interface is fully comp...
2826
0.0
Zero fall-through synchronous FIFO
Fully synchronous FIFO with zero fall-through such that when empty the FIFO behaves like a single stage register....
2827
0.0
Single- and double-precision IEEE-754 floating-point unit
The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu...
2828
2.2581
40Mbps LVDS IO
40Mbps LVDS IO...