851 50.0

DDR5 PHY in TSMC (N5, N4P, N4C, N3P, N3E) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

852 10.0

DDR5 PHY in Samsung (SF4X) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

853 10.0

DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

854 10.0

DDR5/4 PHY in GF (12nm) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

855 10.0

DDR5/4 PHY V2 in TSMC (N7, N6, N5) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

856 20.0

HBM3 PHY (Hard 1) in TSMC (N7, N6, N5) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

857 20.0

HBM3 PHY in TSMC (N5, N6, N7) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

858 50.0

HBM3 PHY V2 in TSMC (N5, N4P, N3E) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

859 10.0

DDR4/3 PHY in TSMC (12nm, 16nm, 7nm) The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...

860 40.0

eMMC 5.1 Device Controller Arasan's eMMC 5.1 Memory controller is compliant with the latest eMMC 5.1 specification released by JEDEC. The controller provides a peak bandwidth of...

861 20.0

LPDDR4 multiPHY V2 in GF (22nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

862 20.0

LPDDR4X multiPHY in Samsung (14nm, 11nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

863 20.0

LPDDR4X multiPHY in GF (14nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

864 20.0

LPDDR4X multiPHY Plus in GF (12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

865 20.0

LPDDR5/4/4X PHY in GF (12nm) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

866 20.0

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

867 30.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

868 50.0

LPDDR5X/5/4X PHY in TSMC (N5, N4P, N4C, N3E, N3P, N3A) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

869 20.0

LPDDR5X/5/4X PHY in Samsung (8nm, SF4X, SF2) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

870 10.0

SD/eMMC in GF (12nm) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

871 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...

872 0.0

LPDDR4 multiPHY V2 in UMC (28nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

873 0.0

DDR5 PHY for SS SF4X The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

874 3.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

875 0.0

HBM3 PHY on TSMC N3P The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

876 0.0

DDR5 MRDIMM2 PHY in Samsung (SF2P) The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products ...

877 0.0

HBM3 PHY IP for TSMC N7 The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

878 15.0

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating...

879 0.0

DDR5 PHY IP for TSMC N3P The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

880 0.0

LPDDR5X/5/4X PHY IP on TSMC N3P The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

881 3.0

GDDR6 PHY IP for GF12LPP The UniIC GDDR6 PHY，subsequently referred to as the UNIIC_GD6PHY, is designed for performance and power efficiency, its target is to deliver industry...

882 25.0

HBM4, HBM3E PHY & Controller INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...

883 60.0

UCIe Chiplet PHY & Controller INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...

884 0.0

MRDIMM DDR5 & DDR5/4 PHY & Controller INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...

885 2.0

SD 4.0 UHS-II PHY in TSMC 40LP SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

886 0.0

LPDDR4X/4/3/DDR4/3/3L PHY + Controller INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...

887 0.0

PSRAM/RPC PHY & Controller INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring acce...

888 15.0

TSMC 12nm DDR3 and DDR4 Controller and PHY A DDR3/4 combo IP solution fabricated on TSMC 12nm process, integrating both controller and PHY. Supports DDR4 up to 3200Mbps and DDR3 up to 2133Mbps,...

889 10.0

DDR5 Serial Presence Detect (SPD5) Hub Interface The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...

890 10.0

DDR5 Temperature Sensor - TS5111 and TS5110 he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...

891 10.0

DDR5 Power Management IC Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...

892 0.0

DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03 The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...

893 100.0

ApSRAM Controller Mobiveil’s ApSRAM Controller is a highly flexible, low-latency, and low-power IP core designed to serve as a high-performance replacement for traditio...

894 0.0

DDR3/3L/DDR4/LPDDR4 PHY The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-...

895 0.0

DDR4 PHY, 16nm/12nm The DDR4 PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR4 memo...

896 20.0

eMMC 5.1 Host Controller The eMMC 5.1 Host Controller IP from Arasan Chip Systems is a highly integrated host controller IP solution. This IP handles all of the timing and ...

897 0.0

DDR5/4 COMBO PHY 7nm/6nm The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...

898 0.0

DDR5/4 COMBO PHY U22 The DDR5/4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant D...

899 0.0

LPDDR5/4X COMBO PHY 7nm/6nm The LPDDR5 and LPDDR4x Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI...

900 50.0

ONFI 4.0 NAND Flash Controller & PHY The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP is changing with it. New applications are emerging and innovative IP solu...