851 0.0

TSMC CLN40LPP 40nm DDR5 PHY - 3200Mbps The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...

852 0.3729

1.8V Secondary Oxide DDRx/LPDDRx PHY - UMC 40nm 40ULP Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...

853 0.0

TSMC CLN40LPP 40nm LPDDR3 PHY - 2133Mbps The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...

854 0.0

TSMC CLN40LPP 40nm LPDDR4 PHY - 2933Mbps The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...

855 0.0

TSMC CLN40LPP 40nm LPDDR5 PHY - 3200Mbps The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...

856 3.0

SD Card Host Controller The logiSDHC is the Secure Digital (SD) card Host Controller IP core from the Xylon logicBRICKS IP core library. It is designed to transfer data from...

857 20.0

UHS-II PHY Silicon Library's world-first silicon proven UHS-II PHY supporting 1.56Gbps speed is available in various fabs/nodes, including TSMC6/12/40/85, GF28, ...

858 10.0

UHS-III PHY Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC65 now....

859 0.0

AHB Internal SRAM Controller The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of...

860 0.0

LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...

861 0.0

eMMC Device Controller eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 and HS400 transfer mo...

862 10.0

DDR4 multiPHY in UMC (28nm) The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...

863 28.0

SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller Arasan Chip Systems’ eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and ...

864 50.0

DDR5 PHY in TSMC (N5, N4P, N3P, N3E) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

865 10.0

DDR5 PHY in Samsung (SF2, SF4X) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

866 10.0

DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

867 10.0

DDR5/4 PHY in GF (12nm) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

868 10.0

DDR5/4 PHY V2 in TSMC (N7, N6, N4C, N5) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

869 25.0

HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5) The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...

870 25.0

HBM2E PHY V2 in TSMC (N7, N6, N5) The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...

871 20.0

HBM3 PHY (Hard 1) in TSMC (N6, N5) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

872 20.0

HBM3 PHY in TSMC (N5, N6, N7) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

873 50.0

HBM3 PHY V2 in TSMC (N5, N4P, N3E) The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

874 10.0

DDR4/3 PHY in TSMC (12nm, 16nm, 7nm) The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...

875 40.0

eMMC 5.1 Device Controller Arasan's eMMC 5.1 Memory controller is compliant with the latest eMMC 5.1 specification released by JEDEC. The controller provides a peak bandwidth of...

876 20.0

LPDDR4 multiPHY V2 in GF (22nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

877 20.0

LPDDR4X multiPHY in Samsung (14nm, 11nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

878 20.0

LPDDR4X multiPHY in GF (14nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

879 20.0

LPDDR4X multiPHY Plus in GF (12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

880 20.0

LPDDR5/4/4X PHY in GF (12nm) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

881 20.0

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

882 30.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

883 50.0

LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E, N3P, N3A) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

884 20.0

LPDDR5X/5/4X PHY in Samsung (SF4X, SF2) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

885 10.0

SD/eMMC in GF (12nm) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

886 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...

887 0.0

LPDDR4 multiPHY V2 in UMC (28nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

888 0.0

DDR5 PHY for SS SF4X The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

889 3.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

890 0.0

HBM3 PHY on TSMC N3P The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

891 0.0

DDR5 MRDIMM2 PHY in TSMC (N3P, N2P) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

892 0.0

HBM3 PHY IP for TSMC N7 The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

893 15.0

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating...

894 0.0

DDR5 PHY IP for TSMC N3P The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

895 0.0

LPDDR5X/5/4X PHY IP on TSMC N3P The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

896 3.0

GDDR6 PHY IP for GF12LPP The UniIC GDDR6 PHY，subsequently referred to as the UNIIC_GD6PHY, is designed for performance and power efficiency, its target is to deliver industry...

897 0.0

HBM4/3E PHY & Controller INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...

898 0.0

UCIe Chiplet PHY & Controller INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...

899 0.0

MRDIMM DDR5 & DDR5/4 PHY & Controller INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...

900 2.0

SD 4.0 UHS-II PHY in TSMC 40LP SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...