101 13.0

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...

102 15.0

MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...

103 15.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...

104 25.0

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture ...

105 100.0

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more Multiprotocol SerDes PMA supporting variety of interfaces....

106 16.0

AHB-Lite APB4 Bridge The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...

107 16.0

AHB-Lite Multilayer Switch The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...

108 16.0

APB4 Multiplexer The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...

109 16.0

AHB-Lite General Purpose Memory Module The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...

110 16.0

APB4 General Purpose Input/Output Module The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...

111 16.0

AHB-Lite Timer The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...

112 16.0

RISC-V Compliant Platform Level Interrupt Controller Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...

113 0.0

Display Stream Compression (DSC 1.2) Decoder The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...

114 0.0

Display Stream Compression (DSC 1.2) Encoder The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K....

115 2.5

SATA Host 6G Controller on Kintex 7 The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...

116 0.0

MST Topology Management Stack The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...

117 10.0

MIPI CSI-2 Receiver for FPGA MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor....

118 10.0

MIPI CSI-2 Transmitter for FPGA MIPI CSI-2 Tx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processer...

119 0.0

128 Channel Analog Front-End PMCC_XCM_64X64_A IP block is a 128 channels analog front-end. The IP block consists of 128 variable gain amplifiers (VGAs), 128 2-bit digitizers, bias...

120 0.0

Digital FIR filter with APB interface The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....

121 2.5

SATA 3 Host Controller on ZYNQ The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...

122 0.0

HSIC PHY The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...

123 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

124 0.0

PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...

125 0.0

RapidIO 2.0 PHY & Controller The Innosilicon Serdes Combo PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interf...

126 0.0

SATA 3.0 PHY The INNOSILICON mixed signal SATA3.0 transceiver PHY provides a complete SATA3.0 standard compliant transceiver physical interface solution for delive...

127 0.0

APB Subsystem The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...

128 2.5

SATA Device Controller on Kintex 7 The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...

129 200.0

Compute Express Link (CXL) 3.1 Controller The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6....

130 0.0

PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface f...

131 25.0

MIPI CSI2 Transmit Controller The Veriest Solutions MIPI CSI-2 v1.1 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between ...

132 0.0

SPI to AMBA AHB Master Bridge The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...

133 0.0

AMBA AHB Slave to Local Interface Bridge The Veriest AMBA AHB Slave Bridge Design IP offers a simple solution to provide a bridge between the embedded AMBA AHB bus and a simplified generic lo...

134 0.0

AMBA AHB Simple Master Bridge The Veriest AMBA AHB Simple Master Bridge Design IP provides a bridge between the embedded AMBA AHB bus master and a simplified generic local bus. The...

135 0.0

Register Indirect RAM Access The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devi...

136 0.0

AMBA AXI Performance Monitor The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility ...

137 0.0

AMBA AHB Address Trapper The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order...

138 2.5

ZYNQ SATA 3 AHCI Host Controller with Linux Driver The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...

139 0.0

AMBA AXI Data Writer Spreader The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data ma...

140 0.0

AMBA AXI Data Prefetch Buffer The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM...

141 25.0

MIPI CSI2 v1.3 Transmit Controller The Veriest Solutions MIPI CSI-2 v1.3 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between ...

142 2.0

I2C Master Serial Interface Controller Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be c...

143 2.0

I2C Slave Serial Interface Controller Slave serial interface compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device. ...

144 6.0

MIPI D-PHY Receiver with PPI SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...

145 3.0

Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

146 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

147 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...

148 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

149 2.5

SATA 3 Host Controller on ARRIA V FPGA The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. T...

150 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...