1651 15.0

ASA-ML Serdes IP Core in 22nm The ASA PHY IP Core in 22nm delivers next-generation automotive SerDes connectivity, enabling high-bandwidth, low-latency serial links for advanced au...

1652 0.0

AHB Lite to AXI Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and the...

1653 0.0

APB to AHB-Lite Asynchronous Bridge The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...

1654 0.0

APB I2C Master/Slave Controller The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...

1655 0.0

Interface Controller - PHY IP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

1656 0.0

UCIe Standard Package PHY on Samsung S8LPU The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

1657 0.0

UCIe Standard Package PHY on Samsung S14LPP The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...

1658 0.0

eUSB2 PHY on Samsung SF4X The Embedded USB 2.0 PHY is a High speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. ...

1659 0.0

USB3.2 PHY on Samsung SF4X This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...

1660 0.0

I3C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...

1661 0.0

USB3.2 PHY on Samsung S8LPU This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...

1662 0.0

MIPI CDPHY TX & RX V2.1/V3.0 This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...

1663 0.0

MIPI CDPHY TX & RX V2.1/V3.0 This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...

1664 0.0

JESD204b Deser PHY GF 22FDX/ GF 22FDX-PLUS InCirT offers Deserializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 2x lanes with data rates from 6.375 ...

1665 0.0

JESD204b Ser PHY GF 22FDX/ GF 22FDX-PLUS InCirT offers Serializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 1x lane with data rates from 6.375 Gbp...

1666 0.0

AHB to AXI Bridge IP SmartDV’s AHB to AXI Bridge IP Core provides a seamless interface between AMBA AHB and AXI protocols, enabling smooth integration of legacy AHB-based ...

1667 0.0

APB Multilayer Interconnect IP SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...

1668 0.0

APB to AHB Bridge IP SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...

1669 0.0

APB to AXI Bridge IP SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...

1670 0.0

DMA AXI4-Stream Interface to AXI Memory Map Address Space Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...

1671 0.0

AXI Multilayer Interconnect IP SmartDV’s AXI Multilayer Interconnect IP is a high-throughput, silicon-proven solution designed to manage complex on-chip communication between multip...

1672 0.0

AXI to AHB Bridge IP SmartDV’s AXI to AHB Bridge IP enables seamless interoperability between AMBA AXI and AMBA AHB protocols, allowing efficient data transfer across syst...

1673 0.0

AXI to APB Bridge IP SmartDV’s AXI to APB Bridge IP enables seamless communication between high-performance AXI-based systems and simpler, lower-power APB peripherals. It ...

1674 0.0

AXI to UCIe Bridge IP SmartDV’s AXI to UCIe Bridge IP enables seamless integration between standard AMBA AXI-based SoC architectures and the emerging UCIe (Universal Chiple...

1675 0.0

CHI to UCIe Bridge IP SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universal Chiplet Interconnec...

1676 0.0

CXL 2.x Controller IP SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalab...

1677 0.0

CXL 3.x Controller IP SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-ce...

1678 0.0

CXL to UCIe Bridge IP SmartDV’s CXL to UCIe Bridge IP enables seamless interoperability between Compute Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe)...

1679 0.0

CXS to UCIe Bridge IP SmartDV’s CXS to UCIe Bridge IP enables seamless connectivity between chiplet-based designs and traditional SoC architectures by bridging AMBA CXS int...

1680 0.0

AXI4 Memory Map to AXI4-Stream Bridge Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...

1681 0.0

DisplayPort 2.x Receiver IP SmartDV’s DisplayPort 2.x Receiver IP is a silicon-proven, high-performance solution built to support next-generation display and video applications a...

1682 0.0

DisplayPort 2.x Transmitter IP SmartDV’s DisplayPort 2.x Transmitter IP is a silicon-proven, high-performance solution designed to enable cutting-edge video transmission in consumer...

1683 5.0

PCIe 5.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1684 5.0

PCIe 5.0 PHY (5nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1685 5.0

PCIe 5.0 PHY (4nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1686 4.0

UCIe 2.0 PHY for Standard Package (4nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

1687 0.0

eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3E, N3P, N2P) Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...

1688 0.0

MIPI MPHY Type 1 G6 2TX2RX in Samsung (SF5A, SF2P) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

1689 0.0

UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

1690 0.0

USB2 Device Controller The Synopsys USB 2.0 Device Controller enables ASIC/FPGA designers to implement a complete USB 2.0 Device interface. The USB 2.0 Device supports USB H...

1691 0.0

I3C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...

1692 0.0

HDMI 2.1/DisplayPort eDP 1.4 TX PHY in TSMC (N6C, N4C) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

1693 20.0

eUSB 2.0 PHY IP Arasan Chip Systems, the leading provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 IP. Embedded USB2 (eUSB2) is a new generati...

1694 0.0

Synopsys USB-C 3.1/DP TX PHY for TSMC N4P The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

1695 0.0

I3C Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...

1696 0.0

AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...

1697 0.0

UDP/IP Hardware Protocol Stack - 50G The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...

1698 10.0

USB 3.0 PHY in UMC (65nm, 40nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1699 0.0

UDP/IP Hardware Protocol Stack - 40G The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...

1700 0.0

UDP/IP Hardware Protocol Stack - 25G The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE net...