Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1205 IP
751
0.118
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library...
752
0.118
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library...
753
0.118
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library
UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library...
754
0.118
UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library
UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library...
755
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library...
756
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library...
757
0.118
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library...
758
0.118
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...
759
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...
760
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library...
761
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...
762
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
763
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
764
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
765
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
766
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...
767
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...
768
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...
769
0.118
UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library
UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library...
770
0.118
UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library
UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library...
771
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...
772
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
773
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
774
0.118
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process...
775
0.118
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....
776
0.118
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
777
0.118
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process...
778
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
779
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
780
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...
781
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
782
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
783
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
784
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
785
0.118
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....
786
0.118
Intelligent Energy Controller for voltage and frequency scaling.
Intelligent Energy Controller for voltage and frequency scaling....
787
0.118
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
788
0.118
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....
789
0.118
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....
790
0.118
Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process
Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process...
791
0.118
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process...
792
0.118
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process...
793
0.118
APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
Synchronous serial port interface controller with APB interface....
794
0.118
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...
795
0.118
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...
796
0.118
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implem...
797
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
798
0.0
4 Gbps DDR CML receiver and transmitter
055TSMC_CML_01 is a library including: - CML receiver (CML_RX); - CML transmitter (CML_TX). The CML_RX block is intended to receive a CML signal a...
799
0.0
1 to 20 MHz Phase-frequency detector and charge pump
Phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator s...
800
0.0
3 to 5 GHz LNA with 2.8dB NF and 20dB gain
130iHP_LNA_04 consists of two bipolar amplifier stages. The block is used correction circuit for frequency range extension. Amplifier output based on ...