Accord Software and Systems Pvt Ltd IP Cores

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1701

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...

1702

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...

1703

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35)...

1704

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)...

1705

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)...

1706

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)...

1707

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)...

1708

0.118

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)

UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)...

1709

0.118

UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair

UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair...

1710

0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library...

1711

0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track generic core cell library

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track generic core cell library...

1712

0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 HVT)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 HVT)...

1713

0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 HVT)

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 HVT)...

1714

0.118

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1715

0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library...

1716

0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library...

1717

0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 LVT)...

1718

0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 LVT)...

1719

0.118

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1720

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...

1721

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track generic cell library...

1722

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 12-track powerslash_core library...

1723

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library...

1724

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track generic core cell library...

1725

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with LMINUS (C31 RVT)...

1726

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Genernic Core cell library with with LPLUS (C38 RVT)...

1727

0.118

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library

UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track Power Slash cell library...

1728

0.118

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.05V Analog ESD IO cell Library...

1729

0.118

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library...

1730

0.118

UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library...

1731

0.118

UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library...

1732

0.118

UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library

UMC 28nm Logic and Mixed-Mode HPC Process,0.9V Analog ESD IO cell Library...

1733

0.118

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library...

1734

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process 1.8V BOAC I/O Cell library...

1735

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library...

1736

0.118

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library

UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V Low Power Low Frequency OSC IO Cell Library...

1737

0.118

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...

1738

0.118

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral

UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...

1739

0.118

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library...

1740

0.118

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...

1741

0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

1742

0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

1743

0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

1744

0.118

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

1745

0.118

UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...

1746

0.118

UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias

UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...

1747

0.118

UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias

UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...

1748

0.118

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library...

1749

0.118

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library...

1750

0.118

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...

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