Design & Reuse
Catalog of SIP Cores
System on Chip design resources
694 IP
51
9.5077
PCIe 5.0 PHY (5nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...
52
9.5077
PCIe 5.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...
53
9.5077
PCIe 6.0 PHY (4nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...
54
9.5077
PCIe 6.0 PHY (5nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...
55
9.5077
PCIe 6.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.x specification. This IP offers a cost-effective and low-power so...
56
9.5077
PCIe 6.x and 56G Ethernet Combo PHY (8nm)
The SERDES PHY includes the functions of both PCIe PHY and Ehternet PHY. The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe...
57
9.0308
UCIe 2.0 PHY for Standard Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
58
8.5077
56G Ethernet PHY (8nm)
The Ethernet PHY IP consists of hardmacro PMA, PMD and softmacro PCS compliant to IEEE 802.3 Ethernet specification. This IP offers a cost-effective a...
59
8.5077
UCIe 2.0 PHY for Advanced Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...
60
8.5077
UCIe 2.0 PHY for Advanced Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
61
8.5077
UCIe 2.0 PHY for Standard Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
62
8.5077
UCIe 2.0 PHY for Standard Package (5nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
63
8.5077
PCIe 4.0 PHY (4nm)
The Qualitas' 4nm PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective an...
64
8.5077
PCIe 4.0 PHY (5nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
65
8.5077
PCIe 4.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
66
8.5077
PCIe 4.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
67
8.5077
UCIe Controller for Standard Package
UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversion. The D2D Adapter su...
68
8.0
PCIe 3.0/2.0 PHY
With sophisticated architecture and advanced technology, KNiulink PCIE GEN3/GEN2 PHY IP with PMA and PCS layer is designed for low power and high perf...
69
7.0
JESD204B /204C PHY&MAC
With sophisticated architecture and advanced technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high performance appli...
70
6.5077
MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (2nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
71
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
72
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (5nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
73
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (5nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
74
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
75
6.5077
MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
76
6.5077
MIPI C-PHY TRx 8Gsps (5nm)
The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...
77
6.5077
MIPI C-PHY TRx 8Gsps / D-PHY TRx 9Gbps Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
78
6.5077
MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
79
6.5077
MIPI CSI-2 RX Controller
The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...
80
6.5077
MIPI CSI-2 TX Controller
The Cameta Serial Interface 2 (CSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allianc...
81
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
82
6.5077
MIPI D-PHY TRx (5nm)
The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loop...
83
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
84
6.5077
MIPI D-PHY TRx 2.5Gbps (11nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
85
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
86
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
87
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
88
6.5077
MIPI D-PHY TRx 2.5Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
89
6.5077
MIPI D-PHY TRx 4.5Gbps (5nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
90
6.5077
MIPI D-PHY TRx 4.5Gbps (8nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
91
6.5077
MIPI DSI-2 RX Controller
The Display Serial Interface 2 (DSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance ...
92
6.5077
MIPI DSI-2 TX Controller
The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...
93
6.5077
USB Super Speed+ PHY (4nm)
The USB PHY IP consists of a hard macro PMA and soft macro PCS compliant with USB 3.2 specification, supporting SuperSpeed+ (10 Gbps) operation. This ...
94
6.5077
Multi-Standard SerDes PHY (4nm)
The MSS PHY IP consists of a hard macro PMA architecture supporting multi-standard NRZ signaling up to 20 Gbps, compliant with PCIe Gen4, DisplayPort ...
95
6.0
RapidIO PHY
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...
96
6.0
DC/DC buck converter
DCDC-ULP-LS-T22ULL-1.62-3.63-0.6-2.5-01b_TSMC_22_ULL is a Nano power DC-DC converter in TSMC 22ULL with ultra-low quiescent current and high efficienc...
97
5.5077
112Gb/s PAM4 SERDES PHY (14nm)
The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3...
98
5.5077
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
99
5.5077
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
100
5.5077
eDP v1.5a RXPHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...