751 10.0

Bandgap - TSMC CLN3A Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...

752 10.0

Bandgap - TSMC CLN3P Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...

753 10.0

RapidIO VIP and Compliance verification Solution Mobiveil’s RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol. The RapidIO VIP is system ...

754 10.0

CAT Trip Sensor, TSMC N3 The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...

755 10.0

CAT Trip Sensor, TSMC N3EP The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...

756 10.0

CAT Trip Sensor, TSMC N5 The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...

757 10.0

CAT Trip Sensor, TSMC N6 The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...

758 10.0

WAVE521, H.265, HEVC, H.264, AVC video encoder IP for 4K WAVE521 is a 4K multi-format encoder IP to support both HEVC/H.265 and AVC/H.264 video formats. It is capable of encoding HEVC Main/Main 10/Main Sti...

759 10.0

WAVE521CL, H.265, HEVC, H.264, AVC video codec IP for 4K low-cost WAVE521CL is a low-cost 4K codec IP to support HEVC/H.265 and AVC/H.264 video standards. The codec IP is capable of encoding 4K60fps@500MHz with HEV...

760 10.0

WAVE521L, H.265, HEVC, H.264, AVC video encoder IP for 4K low-cost WAVE521L is a low-cost 4K encoder IP to support HEVC/H.265 and AVC/H.264 video standards. The IP core provides high-performance encode capability up t...

761 10.0

WAVE633LC, H.265, HEVC, H.264, AVC, video codec IP for 4K low-cost WAVE633LC is a 4K multi-standard video codec IP that supports HEVC/H.265 and AVC/H.264 video codec standards. WAVE633LC targets Low Cost, so B-frame i...

762 10.0

HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...

763 10.0

HBM3 PHY IP at 7nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

764 10.0

BCH Error Correcting Code ECC BCH code statistics for different `$mm` `$tt` Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC: T...

765 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

766 10.0

PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

767 10.0

PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...

768 10.0

PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

769 10.0

PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

770 10.0

PCIe 4.0 LP PHY in TSMC (N7) for Automotive The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

771 10.0

PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+ Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

772 10.0

PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P) The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

773 10.0

UCIe Die-to-Die Chiplet Controller Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...

774 10.0

PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

775 10.0

PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

776 10.0

PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

777 10.0

PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...

778 10.0

PCIe/HCSL Differential IO Buffer - TSMC 16FFC Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...

779 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

780 10.0

PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+ Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

781 10.0

PCIe3 SSCG PLL - TSMC 12FFC Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

782 10.0

PCIe3 SSCG PLL - TSMC 16FFC Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...

783 10.0

PCIe4 Ethernet SERDES PHY - TSMC N5 Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...

784 10.0

PCIe5 Ref Clock SSCG PLL - TSMC 6FF Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...

785 10.0

SD 3.0 / SDIO 3.0 Combo Device Controller The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...

786 10.0

SD 4.0 Device Controller The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...

787 10.0

SD 4.1 SDIO 4.1 Host Controller IP The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...

788 10.0

SD/eMMC in GF (12nm) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

789 10.0

SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6) To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...

790 10.0

GDDR6 PHY IP for 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

791 10.0

SDIO 3.0 Device Controller Arasan's SDIO 3.0 Device IP is used to implement high-performance SDIO cards that connect to a Host processor over a standard SD bus. The SDIO 3.0 Dev...

792 10.0

HDMI1.4 RX LINK Silicon Library's HDMI1.4b RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....

793 10.0

HDMI1.4 TX LINK Silicon Library's HDMI1.4b TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....

794 10.0

HDMI2.0 RX LINK Silicon Library's HDMI2.0 RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....

795 10.0

HDMI2.0 TX LINK Silicon Library's HDMI2.0 TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....

796 10.0

LDO for CPU Cores - TSMC CLN3A ...

797 10.0

LDO for CPU Cores - TSMC CLN3E ...

798 10.0

LDPC for 5G DVBS2 802.11 Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and co...

799 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...

800 10.0

DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...