Design & Reuse
Catalog of SIP Cores
System on Chip design resources
8768 IP
4451
10.0
Bandgap - TSMC CLN3A
Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...
4452
10.0
Bandgap - TSMC CLN3P
Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...
4453
10.0
RapidIO VIP and Compliance verification Solution
Mobiveil’s RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol. The RapidIO VIP is system ...
4454
10.0
CAT Trip Sensor, TSMC N3
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
4455
10.0
CAT Trip Sensor, TSMC N3EP
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
4456
10.0
CAT Trip Sensor, TSMC N5
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
4457
10.0
CAT Trip Sensor, TSMC N6
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
4458
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
4459
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
4460
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
4461
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
4462
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
4463
10.0
PCIe 4.0 LP PHY in TSMC (N7) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
4464
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
4465
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
4466
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
4467
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
4468
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
4469
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
4470
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
4471
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
4472
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
4473
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
4474
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
4475
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
4476
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
4477
10.0
SD 3.0 / SDIO 3.0 Combo Device Controller
The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...
4478
10.0
SD 4.0 Device Controller
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...
4479
10.0
SD 6.0 UHS-III PHY
Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC 65 now....
4480
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
4481
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
4482
10.0
SDIO 3.0 Device Controller
Arasan's SDIO 3.0 Device IP is used to implement high-performance SDIO cards that connect to a Host processor over a standard SD bus. The SDIO 3.0 Dev...
4483
10.0
HDMI 1.4b RX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b RX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requested features can be added....
4484
10.0
HDMI 1.4b TX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b TX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requeted features can be added....
4485
10.0
HDMI 2.0 RX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 RX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
4486
10.0
HDMI 2.0 TX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 TX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
4487
10.0
LDO for CPU Cores - TSMC CLN3A
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4488
10.0
LDO for CPU Cores - TSMC CLN3E
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4489
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
4490
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
4491
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...
4492
10.0
DDR4 multiPHY in Samsung (14nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
4493
10.0
DDR4 multiPHY in TSMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
4494
10.0
DDR4 multiPHY in UMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
4495
10.0
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
4496
10.0
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
4497
10.0
DDR5 PHY in Samsung (SF2, SF4X)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
4498
10.0
DDR5/4 PHY in GF (12nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
4499
10.0
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
4500
10.0
DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...