Design & Reuse
4951 IP
1201
10.0
MACsec Protocol Engine for 10/100/1000 Ethernet
The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all c...
1202
10.0
CAN Bus Controller with Message Filter (configurable)
CANmodule-IIx is a full functional CAN controller module that contains advanced message filtering, and receive-, and transmit buffers. It is designed ...
1203
10.0
CAN Bus Controller with Message Filter (Mailbox concept)
CANmodule-IIIx is a full functional CAN controller module that supports the concept of mailboxes. It is compliant to the international CAN standard de...
1204
10.0
CAN Bus Controller with Message Filter (Mailbox concept)
CANmodule-III is a full functional CAN controller module that supports the concept of mailboxes. It is compliant to the international CAN standard def...
1205
10.0
Band Gap Voltage Generator - TSMC CLN3E
Analog Bits’ regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro. The output...
1206
10.0
Bandgap - TSMC CLN3A
Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...
1207
10.0
Bandgap - TSMC CLN3P
Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macro. The Integ...
1208
10.0
RapidIO VIP and Compliance verification Solution
Mobiveil’s RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol. The RapidIO VIP is system ...
1209
10.0
CAT Trip Sensor, TSMC N3
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1210
10.0
CAT Trip Sensor, TSMC N3EP
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1211
10.0
CAT Trip Sensor, TSMC N5
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1212
10.0
CAT Trip Sensor, TSMC N6
The Catastrophic Trip Sensor has been specifically designed to protect against thermal runaway and comprises a central hub and a remote thermal sensor...
1213
10.0
WAVE521, H.265, HEVC, H.264, AVC video encoder IP for 4K
WAVE521 is a 4K multi-format encoder IP to support both HEVC/H.265 and AVC/H.264 video formats. It is capable of encoding HEVC Main/Main 10/Main Sti...
1214
10.0
WAVE521CL, H.265, HEVC, H.264, AVC video codec IP for 4K low-cost
WAVE521CL is a low-cost 4K codec IP to support HEVC/H.265 and AVC/H.264 video standards. The codec IP is capable of encoding 4K60fps@500MHz with HEV...
1215
10.0
WAVE521L, H.265, HEVC, H.264, AVC video encoder IP for 4K low-cost
WAVE521L is a low-cost 4K encoder IP to support HEVC/H.265 and AVC/H.264 video standards. The IP core provides high-performance encode capability up t...
1216
10.0
WAVE633LC, H.265, HEVC, H.264, AVC, video codec IP for 4K low-cost
WAVE633LC is a 4K multi-standard video codec IP that supports HEVC/H.265 and AVC/H.264 video codec standards. WAVE633LC targets Low Cost, so B-frame i...
1217
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
1218
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1219
10.0
BCH Error Correcting Code ECC
BCH code statistics for different `$mm` `$tt` Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC: T...
1220
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1221
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
1222
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
1223
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1224
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1225
10.0
PCIe 4.0 LP PHY in TSMC (N7) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1226
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1227
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
1228
10.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
1229
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1230
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1231
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1232
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
1233
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
1234
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1235
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1236
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1237
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
1238
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
1239
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
1240
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
1241
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
1242
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1243
10.0
HDMI1.4 RX LINK
Silicon Library's HDMI1.4b RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
1244
10.0
HDMI1.4 TX LINK
Silicon Library's HDMI1.4b TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
1245
10.0
HDMI2.0 RX LINK
Silicon Library's HDMI2.0 RX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
1246
10.0
HDMI2.0 TX LINK
Silicon Library's HDMI2.0 TX Link IP is the best choice for our PHY IPs. Customer's function can be included on request....
1247
10.0
LDO for CPU Cores - TSMC CLN3A
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1248
10.0
LDO for CPU Cores - TSMC CLN3E
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1249
10.0
LDPC for 5G DVBS2 802.11
Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and co...
1250
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...