Design & Reuse
5514 IP
1301
10.0
Wide Range PLL - TSMC 6FF
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to pro...
1302
10.0
Wide Range PLL - TSMC CLN3P
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to p...
1303
10.0
Wide Range PLL - TSMC N5
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to pro...
1304
10.0
Wide Range Programable Integer PLL - TSMC CLN2P
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to p...
1305
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
1306
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
1307
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
1308
10.0
Differential Clock Receiver - TSMC CLN2P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1309
10.0
Differential Clock Receiver - TSMC CLN3A
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1310
10.0
Differential Clock Receiver - TSMC CLN3E
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1311
10.0
Differential Clock Receiver to CML - TSMC CLN2P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1312
10.0
Differential Clock Receiver to CML - TSMC CLN3A
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1313
10.0
Differential Clock Receiver to CML - TSMC CLN3E
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1314
10.0
Differential Clock Receiver to CML - TSMC CLN6FF
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1315
10.0
Differential Clock Reciever - TSMC CLN3P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1316
10.0
Differential Clock Reciever to CML - TSMC CLN3P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1317
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a...
1318
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1319
10.0
Differential Output Buffer - TSMC CLN3E
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1320
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1321
10.0
Differential Output Buffer - TSMC CLN4P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1322
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1323
10.0
Differential Output Driver - TSMC CLN2P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1324
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1325
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1326
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1327
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1328
10.0
High Performance 20GHz C2C PLL - TSMC CLN3A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1329
10.0
High Performance 20GHz C2C PLL - TSMC CLN3E
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1330
10.0
High Performance 20GHz C2C PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1331
10.0
High Performance 20GHz PLL - TSMC CLN4P
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1332
10.0
High Performance 20GHz PLL - TSMC CLN5A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1333
10.0
High Precision Temp Sensor - TSMC CLN2P
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1334
10.0
High Precision Temp Sensor - TSMC CLN3A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1335
10.0
High Precision Temp Sensor - TSMC CLN3E
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1336
10.0
High Precision Temp Sensor - TSMC CLN5A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1337
10.0
High Speed 20GHz PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1338
10.0
High Speed PLL - TSMC N4P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1339
10.0
High Speed PLL - TSMC N5
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1340
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1341
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1342
10.0
High Speed PLL CML to Complementary - TSMC CLN3P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1343
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
1344
10.0
LIN Bus Master/Slave Controller Core
Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...
1345
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1346
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1347
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1348
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1349
10.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1350
10.0
MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...