Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5510 IP
751
10.0
HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard
Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates wit...
752
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
753
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
754
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
755
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
756
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
757
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
758
10.0
PCIe 4.0 LP PHY in TSMC (N7) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
759
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
760
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
761
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN2P
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
762
10.0
PCIe Gen 4/5/6 Ref Clock SSCG PLL - TSMC CLN7FF
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
763
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3A
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
764
10.0
PCIe Gen4/5 Ref SSCG PLL - TSMC CLN3E
Analog Bits’ PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Ge...
765
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
766
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
767
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
768
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
769
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
770
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
771
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
772
10.0
SD 3.0 / SDIO 3.0 Combo Device Controller
The SD / SDIO 3.0 Combo Device IP Core is a high performance controller capable of interfacing with memory cards and I/O applications such as WLAN, Bl...
773
10.0
SD 4.0 Device Controller
The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP ...
774
10.0
SD 4.1 SDIO 4.1 Host Controller IP
The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...
775
10.0
SD 6.0 UHS-III PHY
Silicon Library's world-first silicon proven UHS-III PHY is available in SMIC 65 now....
776
10.0
SD/eMMC in GF (12nm)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
777
10.0
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for emb...
778
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
779
10.0
SDIO 3.0 Device Controller
Arasan's SDIO 3.0 Device IP is used to implement high-performance SDIO cards that connect to a Host processor over a standard SD bus. The SDIO 3.0 Dev...
780
10.0
HDMI 1.4b RX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b RX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requested features can be added....
781
10.0
HDMI 1.4b TX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b TX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requeted features can be added....
782
10.0
HDMI 2.0 RX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 RX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
783
10.0
HDMI 2.0 TX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 TX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
784
10.0
LDO for CPU Cores - TSMC CLN3A
...
785
10.0
LDO for CPU Cores - TSMC CLN3E
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786
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
787
10.0
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4...
788
10.0
DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
Analog Bits impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today...
789
10.0
DDR4 multiPHY in Samsung (14nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
790
10.0
DDR4 multiPHY in TSMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
791
10.0
DDR4 multiPHY in UMC (28nm)
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), an...
792
10.0
DDR4/3 PHY in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
793
10.0
DDR4/3 PHY in TSMC (12nm, 16nm, 7nm)
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) application...
794
10.0
DDR5 PHY in Samsung (SF4X)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
795
10.0
DDR5/4 PHY in GF (12nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
796
10.0
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
797
10.0
DDR5/4 PHY in TSMC (16nm, 12nm, N6, N7, N5)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
798
10.0
DDR5/4 PHY V2 in TSMC (N7, N6, N5)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
799
10.0
Secure Boot Software Development Kit
Secure boot enhances the security of an embedded system by cryptographically verifying that the code being loaded and executed is authentic and has no...
800
10.0
Security Protocol Accelerator for SM3 and SM4
SM3 and SM4 are commercial cryptographic standards issued and regulated by the Chinese Office of State Commercial Cryptography Administration (OSCCA)...