451 3.0

IEEE 802.1ae (MACsec) Security Processor Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...

452 3.0

Generic CCM AES Core The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in inte...

453 3.0

Generic CCM AES Core with CMAC Option The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated input...

454 3.0

AES IP Core Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...

455 3.0

SHA1, SHA2 Cryptographic Hash Cores The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through”...

456 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

457 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

458 3.0

High-Performance Lossless Compression Core Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

459 3.0

High-Performance Lossless Compression/Encryption Combo Core Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

460 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

461 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

462 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

463 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

464 3.0

Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

465 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...

466 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

467 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

468 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

469 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

470 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

471 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

472 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

473 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...

474 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

475 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

476 3.0

MIPI RFFE Master IP SmartDV’s MIPI RFFE (Radio Frequency Front-End) Master IP is a silicon-proven solution designed for high-speed, low-latency control of RF front-end co...

477 3.0

MIPI SPMI Slave IP SmartDV’s MIPI SPMI (System Power Management Interface) Slave IP is a silicon-proven solution tailored for efficient communication with power manageme...

478 3.0

NIST AES Key Wrap/Unwrap Core AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...

479 3.0

Elliptic Curve Point Multiply and Verify Core Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...

480 3.0

Ultra-Compact 3GPP Cipher Core The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...

481 3.0

Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...

482 3.0

Ultra-Compact Data Encryption Standard (DES/3DES) Core The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....

483 3.0

SNOW 3G Encryption Core The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...

484 3.0

Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40uLPeF METRO-PM-MFE-mono.11-HD-IVT_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resoluti...

485 3.0

Complete measurement analog front end (AFE) IP for three-phase power metering in SMIC 40LL-RF METRO-PM-JADE-3P.11-HD_SMIC_40_LL-RF is a Mixed signal (analog and digital) Virtual Component in SMIC 40LL-RF which offers a complete analog front-end...

486 3.0

Complete measurement analog front end (AFE) IP for three-phase power metering in TSMC 40uLPeF METRO-PM-JADE-3P.11-HD_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resolution Mi...

487 3.0

complete measurement subsystem IP for single phase power meteringi in HHGrace 130eF Metro-Jade-PM-mono-10-HD-OV_HHGrace_130_eF is a Mixed signal (analog and digital) Virtual Component in HHGrace 130eF which offers a complete analog fr...

488 3.0

FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA) FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) ...

489 3.0

FortifyIQ Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA) FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms, such as RSA and ECC, with post-quantum standards including ML-KEM ...

490 3.0

FortifyIQ's Compact DPA and FIA Hardened Post-Quantum ML-KEM IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant) As quantum computing threatens traditional public-key cryptography, resource-constrained devices must adopt quantum-resistant algorithms without compr...

491 3.0

FortifyIQ's Compact Post-Quantum ML-DSA Secure Cryptographic Signature IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant) As digital signature algorithms face obsolescence in the quantum era, embedded systems require quantum-resistant alternatives that balance performance...

492 3.0

LPDDR2/3/4/4x IP combo solution with high performance and low power With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...

493 3.0

True Random and Pseudorandom Number Generator The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...

494 3.0

LRW-AES Core Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....

495 3.0

LRW-AES Core LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...

496 3.0

LRW-AES Core Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...

497 3.0

Cryptographically Secure Pseudo Random number Generator IP Core The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...

498 3.0

RSA Public Key Exponentiation Accelerator Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...

499 3.0

USB 2.0 (LS, FS & HS) On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...

500 3.0

SSL/TLS Processor IP Core with an AXI Bus Interface The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...