Design & Reuse
906 IP
51
14.0
MIPI CSI-2 TX Controller for v2.1
CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance ...
52
14.0
MIPI D-PHY for TSMC
D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, ...
53
14.0
MIPI DSI TX Controller
DSI transmitter controller for application The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance Specificatio...
54
14.0
UltraLink Controller
Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...
55
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
56
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
57
14.0
Controller for MIPI Soundwire
Audio data transport The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance required...
58
14.0
USB 2.0 Controller
Mature controller solution for OTG and Device applications Certified for compliance with Universal Serial Bus Specification, Revision 2.0, the Cadenc...
59
14.0
USB 2.0 PHY for TSMC
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...
60
14.0
USB 3.0 xHCI Host Controller
Mature solutions featuring xHCI Host, Device, and Dual-Role Device Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 and xHCI Speci...
61
14.0
USB 3.1 Device Controller
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...
62
14.0
USXGMII Ethernet PCS (PCSR_X)
The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any system on chip (SoC). The...
63
14.0
Ethernet XAUI PCS
Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the logic required to in...
64
14.0
Dual-Role Device Controller for USB 3.0
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.0 Specification v1.0, and xHCI Specification v1.0, th...
65
14.0
Dual-Role Device Controller for USB 3.1
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, th...
66
14.0
CXL Controller
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Cadence® Controller IP for CXL provides the logic r...
67
0.0
30G MR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challengings applications The ...
68
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
69
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
70
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
71
0.0
112G-ULR PAM4 SerDes PHY for Samsung SF5A
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
72
0.0
112G-ULR PAM4 SerDes PHY for TSMC N3E/N3P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
73
0.0
112G-ULR PAM4 SerDes PHY for TSMC N5/N4P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
74
0.0
112G-ULR PAM4 SerDes PHY for TSMC N6/N7
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
75
0.0
112G-VSR for TSMC N3E/N3P
112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
76
0.0
224G-LR SerDes PHY for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...
77
0.0
224G-LR SerDes PHY for UALink for Intel 18A
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up net...
78
0.0
224G-LR SerDes PHY for UALink for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up netwo...
79
0.0
32G LR Multi-Protocol SerDes (MPS) PHY
Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure The 32G MPS...
80
0.0
32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
81
0.0
16G Ethernet SerDes PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
82
0.0
16G Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
83
0.0
16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
84
0.0
16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
85
0.0
16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
86
0.0
16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
87
0.0
16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
88
0.0
16G UCIe Standard PHY for TSMC N5A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
89
0.0
16G UCIe Standard PHY for TSMC N7
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
90
0.0
56G-LR Pam4 SerDes for TSMC N6/N7
56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G The Cadence 56Gbps Long...
91
0.0
28G LR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 2...
92
0.0
PCI Express (PCIe) 6.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...
93
0.0
PCI Express (PCIe) 7.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...
94
0.0
PCIe 4/3/2 SerDes PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
95
0.0
GDDR6 Memory PHY for TSMC N5P
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
96
0.0
GDDR6 Memory PHY for TSMC N7
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
97
0.0
GDDR6 PHY for TSMC N6
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
98
0.0
GDDR7 Memory PHY for TSMC N3P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
99
0.0
GDDR7 Memory PHY for TSMC N4P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
100
0.0
GDDR7 Memory PHY for TSMC N5P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...