Design & Reuse
3912 IP
3651
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler....
3652
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um Logic HS FSG Synchronous high density Low Power Two Port Register File SRAM memory compiler....
3653
0.118
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous Two Port Register File SRAM memory compiler....
3654
0.118
Two Port Register File Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous Two Port Register File SRAM memory compiler....
3655
0.118
Two Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3656
0.118
Two Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3657
0.118
Two Port Register File Compiler IP, UMC 0.162um Logic process
UMC 0.162um Logic process synchronous Two Port Register File SRAM memory compiler....
3658
0.118
Two Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3659
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Two Port Register File compiler....
3660
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3661
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
3662
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3663
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3664
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
3665
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
3666
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3667
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
3668
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
3669
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Two Port Register File compiler....
3670
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP peripheral LVT Two Port Register File memory compiler....
3671
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....
3672
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT....
3673
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....
3674
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....
3675
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler....
3676
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler....
3677
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler....
3678
0.118
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler....
3679
0.118
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler....
3680
0.118
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler....
3681
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler....
3682
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler....
3683
0.118
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implem...
3684
0.118
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface....
3685
0.118
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect....
3686
0.118
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge....
3687
0.118
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller....
3688
0.118
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface....
3689
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
3690
0.118
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface. Faraday's FTINTC030 Generic interrupt controller supports software generated interrupt, private perip...
3691
0.118
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process....
3692
0.118
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS...
3693
0.0
1 Port High-Current Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
1 Port Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
3694
0.0
2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
3695
0.0
1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
3696
0.0
a robust lighting control technology based on the globally interoperable Bluetooth mesh standard.
We provide a robust lighting control technology based on the globally interoperable Bluetooth mesh standard. Whether you are a component manufacturer,...
3697
0.0
4-/8-bit mixed-precision NPU IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
3698
0.0
1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency
Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...
3699
0.0
5-60V Input Buck Regulator (Type-C EPR compatible)
The OT1152 is an 80mA CMOS buck regulator designed for use with high input voltages and logic level output voltages.. This implementation takes a 4...
3700
0.0
8-bit micro-controller high speed 4clk/machine cycle architecture256 bytes of on-chip Data RAM,Three 16-bit timer/countersTwo 16-bit dptr
8-bit micro-controller high speed 4clk/machine cycle architecture256 bytes of on-chip Data RAM,Three 16-bit timer/countersTwo 16-bit dptr...