Design & Reuse
3908 IP
2551
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
2552
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
2553
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2554
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
2555
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2556
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell....
2557
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2558
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....
2559
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...
2560
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2561
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2562
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...
2563
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...
2564
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2565
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
2566
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2567
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2568
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....
2569
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
2570
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...
2571
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2572
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....
2573
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
2574
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...
2575
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2576
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....
2577
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
2578
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
2579
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
2580
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
2581
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
2582
0.118
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias...
2583
0.118
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias...
2584
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
2585
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
2586
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...
2587
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....
2588
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
2589
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
2590
0.118
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
2591
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell....
2592
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...
2593
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....
2594
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
2595
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
2596
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
2597
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2598
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2599
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2600
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....